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參數(shù)資料
| 型號： | ASM5I9351 |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| 中文描述： | 2.5V或3.3V，200兆赫，9輸出零延遲緩沖器 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 522K |
| 代理商： | ASM5I9351 |
July 2005
rev 0.2
ASM5I9351
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Features
Output frequency range: 25 MHz to 200 MHz
Input frequency range: 25 MHz to 200 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
± 2.5% max Output duty cycle variation
Nine Clock outputs: Drive up to 18 clock lines
Two reference clock inputs: LVPECL or LVCMOS
150-ps max output-output skew
Phase-locked loop (PLL) bypass mode
‘SpreadTrak’
Output enable/disable
Pin-compatible with MPC9351 and CY29351.
Industrial temperature range: –40°C to +85°C
32-pin 1.0mm TQFP & LQFP Package.
Functional Description
The ASM5I9351 is a low voltage high performance
200MHz PLL-based zero delay buffer designed for high
speed clock distribution applications.
The ASM5I9351 features LVPECL and LVCMOS reference
clock inputs and provides 9 outputs partitioned in 4 banks
of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by
2 or 4 while the other banks divide by 4 or 8 per SEL(A:D)
settings, see Table.2. These dividers allow output to input
ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each LVCMOS
compatible output can drive 50
series or parallel
terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured
to run between 200 MHz to 500 MHz. This allows a wide
range of output frequencies from 25 MHz to 200 MHz. For
normal operation, the external feedback input, FB_IN, is
connected to one of the outputs. The internal VCO is
running at multiples of the input reference clock set by the
feedback divider, see the Table 1.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
does not apply.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9351-32-ET | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351-32-LT | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9352G-32-ET | CONNECTOR ACCESSORY |
| ASM5I9352G-32-LT | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| ASM5I9352 | 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9351-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351G-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351G-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9352 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
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