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參數(shù)資料
| 型號(hào)： | ASM5I9350G-32-LT |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Mechanism, 2-inch, front feed, w/ manual knob, platen detect & cutter (full cut) |
| 中文描述： | 200 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | GREEN, LQFP-32 |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大小： | 473K |
| 代理商： | ASM5I9350G-32-LT |
July 2005
rev 0.2
Pin Discription
1
ASM5I9350
3.3V 1:10 LVCMOS PLL Clock Generator
3 of 12
Notice: The information in this document is subject to change without notice.
Pin #
Pin Name
XOUT
I/O
O
Type
Analog
Description
8
Oscillator Output
. Connect to a crystal.
Oscillator Input
. Connect to a crystal.
LVCMOS/LVTTL reference clock input
Clock output bank A
Clock output bank B
Clock output bank C
9
XIN
I
Analog
30
TCLK
I, PD
LVCMOS
28
QA
O
LVCMOS
26
QB
O
LVCMOS
22, 24
12, 14, 16,
18, 20
2
QC(1:0)
O
LVCMOS
QD(4:0)
O
LVCMOS
Clock output bank D
FB_SEL
I, PD
LVCMOS
Internal Feedback Select Input
. See
Table 1
.
Output enable/disable input
. See
Table 2
.
PLL enable/disable input
. See
Table 2
.
Reference select input
. See
Table 2
.
Frequency select input, Bank (A:D)
. See
Table 2
.
2.5V or 3.3V Power supply for bank B output clock
2,3
2.5V or 3.3V Power supply for bank C output clocks
2,3
2.5V or 3.3V Power supply for bank D output clocks
2,3
2.5V or 3.3V Power supply for PLL
2,3
2.5V or 3.3V Power supply for core, inputs, and bank A
output clock
2,3
Analog ground
10
OE#
I, PD
LVCMOS
31
PLL_EN
I, PU
LVCMOS
32
3, 4, 5, 6
27
23
15, 19
1
REF_SEL
SEL(A:D)
VDDQB
VDDQC
VDDQD
AVDD
I, PD
I, PD
Supply
Supply
Supply
Supply
LVCMOS
LVCMOS
VDD
VDD
VDD
VDD
11
VDD
Supply
VDD
7
13, 17, 21,
25, 29
Note: 1. PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1μF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins
their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output
power supply pins.
AVSS
Supply
Ground
VSS
Supply
Ground
Common ground
Table 1: Frequency Table
FB_SEL
Feedback Divider
VCO
Input Frequency
Range (AVDD = 3.3V)
6.25 MHz to 15.625 MHz
Input Frequency
Range (AVDD = 2.5V)
6.25 MHz to 11.875 MHz
0
÷32
Input Clock * 32
1
÷16
Input Clock * 16
12.5 MHz to 31.25 MHz
12.5 MHz to 23.75 MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9350 | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9350-32-ET | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9350-32-LT | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9351G-32-ET | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351G-32-LT | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9351 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351G-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351G-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
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