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參數(shù)資料
| 型號： | ASM5I9350-32-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 3.3V 1:10 LVCMOS PLL Clock Generator |
| 中文描述： | 200 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | 1 MM HEIGHT, TQFP-32 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 473K |
| 代理商： | ASM5I9350-32-ET |
July 2005
rev 0.2
ASM5I9350
3.3V 1:10 LVCMOS PLL Clock Generator
7 of 12
Notice: The information in this document is subject to change without notice.
AC Electrical Specifications
(VCC = 3.3V ± 5%, TA = -40°C to +85°C)
1
Parameter
f
VCO
Description
Condition
Min
200
12.5
6.25
Typ
-
-
-
Max
500
31.25
15.625
Unit
MHz
VCO Frequency
÷16 Feedback
÷32 Feedback
Bypass mode
(PLL_EN = 0)
0.8V to 2.0V
÷2 Output
÷4 Output
÷8 Output
f
MAX
< 100 MHz
f
MAX
> 100 MHz
0.8V to 2.4V
Banks at same voltage
Banks at different voltages
÷16 Feedback
f
in
Input Frequency
0
-
200
MHz
f
XTAL
f
refDC
t
r
, t
f
Crystal Oscillator Frequency
Input Duty Cycle
TCLK Input Rise/FallTime
10
25
-
100
50
25
47.5
45
0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
25
75
1.0
200
125
62.5
52.5
55
1.0
150
350
10
10
-
MHz
%
nS
f
MAX
Maximum Output Frequency
MHz
DC
Output Duty Cycle
%
t
r
, t
f
t
sk(O)
t
sk(B)
t
PLZ, HZ
t
PZL, ZH
Output Rise/Fall times
Output-to-Output Skew
Bank-to-Bank Skew
Output Disable Time
Output Enable Time
nS
pS
pS
nS
nS
0.7 – 0.9
BW
PLL Closed Loop Bandwidth (–3dB)
÷32 Feedback
-
0.6 – 0.8
-
MHz
Same frequency
-
-
150
t
JIT(CC
)
Cycle-to-Cycle Jitter
Multiple frequencies
-
-
250
pS
Same frequency
-
-
100
t
JIT(PER)
Period Jitter
Multiple frequencies
-
-
150
pS
t
LOCK
Note: 1. AC characteristics apply for parallel output termination of 50
to V
TT
. Parameters are guaranteed by characterization and are not 100% tested.
Maximum PLL Lock Time
-
-
1
mS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9350-32-LT | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9351G-32-ET | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351G-32-LT | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351 | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351-32-ET | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9350-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9350G-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9350G-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9351 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
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