- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381376 > ASM5I9350-32-ET (ALLIANCE SEMICONDUCTOR CORP) 3.3V 1:10 LVCMOS PLL Clock Generator PDF資料下載
參數(shù)資料
| 型號(hào)： | ASM5I9350-32-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 3.3V 1:10 LVCMOS PLL Clock Generator |
| 中文描述： | 200 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | 1 MM HEIGHT, TQFP-32 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 473K |
| 代理商： | ASM5I9350-32-ET |
July 2005
rev 0.2
DC Electrical Specifications
(V
CC
= 2.5V ± 5%, T
A
= -40°C to +85°C)
ASM5I9350
3.3V 1:10 LVCMOS PLL Clock Generator
5 of 12
Notice: The information in this document is subject to change without notice.
Parameter
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
I
DDA
I
DDQ
Description
Condition
Min
-
1.7
-
1.8
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
5
-
180
210
4
Max
0.7
V
DD
+0.3
0.6
-
-100
100
10
7
-
-
-
Unit
V
V
V
V
μA
μA
mA
mA
Input Voltage, Low
Input Voltage, High
Output Voltage, Low
1
Output Voltage, High
1
Input Current, Low
2
Input Current, High
2
PLL Supply Current
Quiescent Supply Current
LVCMOS
LVCMOS
I
OL
= 15mA
I
OH
= –15mA
V
IL
= V
SS
V
IL
= V
DD
AVDD only
All VDD pins except AVDD
Outputs loaded @ 100 MHz
Outputs loaded @ 200 MHz
I
DD
Dynamic Supply Current
mA
C
IN
Input Pin Capacitance
pF
Z
OUT
Note: 1. Driving one 50
parallel terminated transmission line to a termination voltage of V
TT
. Alternatively, each output drives up to two 50
series terminated
transmission lines.
2. Inputs have pull-up or pull-down resistors that affect the input current.
Output Impedance
14
18
22
DC Electrical Specifications
(V
CC
= 3.3V ± 5%, T
A
= -40°C to +85°C)
Parameter
V
IL
V
IH
Description
Condition
Min
-
2.0
-
-
2.4
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
5
-
270
300
4
Max
0.8
V
DD
+0.3
0.55
0.30
-
–100
100
10
7
-
-
-
Unit
V
V
Input Voltage, Low
Input Voltage, High
LVCMOS
LVCMOS
I
OL
= 24 mA
I
OL
= 12 mA
I
OH
= –24 mA
V
IL
= V
SS
V
IL
= V
DD
AVDD only
All VDD pins except AVDD
Outputs loaded @ 100 MHz
Outputs loaded @ 200 MHz
V
OL
Output Voltage, Low
1
V
V
OH
I
IL
I
IH
I
DDA
I
DDQ
Output Voltage, High
1
Input Current, Low
2
Input Current, High
2
PLL Supply Current
Quiescent Supply Current
V
μA
μA
mA
mA
I
DD
Dynamic Supply Current
mA
C
IN
Input Pin Capacitance
pF
Z
OUT
Note: 1. Driving one 50
parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50
series terminated
transmission lines.
2. Inputs have pull-up or pull-down resistors that affect the input current.
Output Impedance
12
15
18
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9350-32-LT | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9351G-32-ET | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351G-32-LT | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351 | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351-32-ET | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9350-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9350G-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9350G-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9351 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
| ASM5I9351-32-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。