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參數(shù)資料
| 型號： | ASM4SSTVF32852 |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | DDR 24-Bit to 48-Bit Registered Buffer |
| 中文描述： | 復(fù)員24位到48位注冊緩沖區(qū) |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 105K |
| 代理商： | ASM4SSTVF32852 |
August
2004
ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer
9 of 13
t
w
Input
V
IH
V
IL
V
REF
V
REF
Input
V
IH
V
IL
V
REF
V
REF
V
ICR
Timing input
t
s
t
h
V
I(pp)
Parameter Measurement Information (V
DD
= 2.5 V ± 0.2V)
V
TT
R
L
= 50
Test point
C
L
= 30 pF
1
Load circuit
From output under test
1
C
L
includes probe and jig capacitance.
Voltage and Current Waveforms
In the following waveforms, note that all input pulses are supplied by generators having the following characteristics:
PRR
10 MHz, Z
o
= 50
, input slew rate = 1 V/ns ± 20% (unless otherwise specified).
The outputs are measured one at a time with one transition per measurement.
V
TT
= V
REF
= V
DDQ
/2.
V
IH
= V
REF
+ 310 mV (AC voltage levels) for differential inputs. V
IH
= V
DD
for LVCMOS input.
V
IL
= V
REF
- 310 mV (AC voltage levels) for differential inputs. V
IL
= GND for LVCMOS input.
t
PLH
and t
PHL
are the same as t
pd
.
Input active and inactive times
LVCMOS RESETB
I
DD1
1
I
DD
tested with clock and data inputs held at V
DD
or GND, and I
O
= 0 mA.
V
DD
0 V
I
DDH
I
DDL
V
DD
/2
10%
V
DD
/2
90%
t
inact
t
act
Input
Pulse duration
Setup and hold times
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| ASM4ISSTVF32852-114BT | DDR 24-Bit to 48-Bit Registered Buffer |
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|---|---|
| ASM4SSTVF32852-114BR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:DDR 24-Bit to 48-Bit Registered Buffer |
| ASM4SSTVF32852-114BT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:DDR 24-Bit to 48-Bit Registered Buffer |
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