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參數(shù)資料
| 型號： | ASM4SSTVF32852 |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | DDR 24-Bit to 48-Bit Registered Buffer |
| 中文描述： | 復(fù)員24位到48位注冊緩沖區(qū) |
| 文件頁數(shù)： | 7/13頁 |
| 文件大小： | 105K |
| 代理商： | ASM4SSTVF32852 |
August
2004
ASM4SSTVF32852
rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer
7 of 13
DC Electrical Characteristics
T
A
= 0°C to 70°C, V
DD
= 2.5 ± 0.2V, and V
DDQ
= 2.5±0.2V (unless otherwise stated)
Guaranteed by design. Not 100% production tested.
Symbol
Parameter
Test conditions
V
DDQ
Min
Typ
Max
Units
V
IK
I
I
= -18 mA
2.3 V
-1.2
V
I
OH
= -100
A
2.3 V to 2.7 V
V
DD
- 0.2
V
V
OH
I
OH
= -16 mA
2.3 V
2.05
V
I
OL
= 100
A
2.3 V to 2.7 V
0.2
V
V
OL
I
OL
= 16 mA
2.3 V
0.20
V
I
I
All inputs
V
I
= V
DD
or GND
2.7 V
± 5
A
Standby
(static)
RESETB = GND
0.01
A
I
DD
Operating
(static)
V
I
= V
IH(AC)
or V
IL(AC)
,
RESETB = V
DD
40
mA
Dynamic
operating
(clock only)
RESETB = V
DD
,
V
I
= V
IH(AC)
or V
IL(AC)
,
CLK and CLKB switching
50% duty cycle
35
A/clock
MHz
I
DDD
Dynamic
operating
(per each
data input)
RESETB = V
DD
, V
I
= V
IH(AC)
or
V
IL(AC)
, CLK and CLKB =
switching 50% duty cycle;
One data input switching at half
clock frequency, 50% duty cycle
I
O
= 0
2.5V
7
/clock
MHz/data
input
r
OH
Output high
I
OH
= -20 mA
2.3 V to 2.7 V
12
r
OL
Output low
I
OL
= 20 mA
2.3 V to 2.7 V
10
r
O(D)
|r
OH
- r
OL
|
each
separate bit
I
O
= 20 mA, T
A
= 25
C
2.5 V
4
Data inputs
2.5 V
2.5
3.5
pF
C
i
CLK & CLKB
V
I
= V
REF
± 350 mV, V
ICR
= 1.25 V,
V
I(PP)
= 360 mV
2.5 V
2.5
3.5
pF
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| ASM4ISSTVF32852-114BT | DDR 24-Bit to 48-Bit Registered Buffer |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ASM4SSTVF32852-114BR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:DDR 24-Bit to 48-Bit Registered Buffer |
| ASM4SSTVF32852-114BT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:DDR 24-Bit to 48-Bit Registered Buffer |
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