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參數(shù)資料
| 型號(hào)： | ASM4SSTVF32852-114BR |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | DDR 24-Bit to 48-Bit Registered Buffer |
| 中文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA114 |
| 封裝： | BGA-114 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 105K |
| 代理商： | ASM4SSTVF32852-114BR |
August
2004
ASM4SSTVF32852
rev 2.0
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
DDR 24-Bit to 48-Bit Registered Buffer
Features
Differential clock signals.
Supports SSTL_2 class II specifications on
inputs and outputs.
Low voltage operation.
V
DD
= 2.3V to 2.7V.
Available in 114 ball BGA package.
Industrial temperature range also available.
Product Description
The 24-Bit to 48-Bit ASM4SSTVF32852 is a universal
bus driver designed for 2.3V to 2.7V V
DD
operation and
SSTL_2 I/O levels except for the LVCMOS RESETB
input.
Data flow from D to Q is controlled by the differential
clock (CLK/CLKB) and a control signal (RESETB). The
positive edge of CLK is used to trigger the data flow,
and CLKB is used to maintain sufficient noise margins,
whereas the RESETB, an LVCMOS asynchronous
signal is intended for use at the time of power-up only.
The ASM4SSTVF32852 supports a low power standby
mode of operation. A logic
“Low” level at RESETB,
assures that all internal registers and outputs (Q) are
reset to a logic “Low” state, and that all input receivers,
data (D) buffers, and clock (CLK/CLKB) are switched
off. Please note that RESETB must always be
supported with a LVCMOS levels at a valid logic state
since VREF may not be stable during power-up.
To ensure that outputs are at a defined logic state
before a stable clock has been supplied, RESETB must
be held at a logic “Low” level during power-up.
In the DDR DIMM application, RESETB is specified to
be asynchronous with respect to CLK/CLKB. Therefore,
no timing relationship can be guaranteed between the
two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be
driven to a logic “Low” level quickly relative to the time
to disable the differential input receivers. This ensures
there are no “glitches” on any output. However, when
coming out of low power standby state, the register will
become active quickly relative to the time taken to
enable the differential input receivers. When the data
inputs are at a logic level “Low” and the clock is stable
during the “Low-to-High” transition of RESETB until the
input receivers are fully enabled, the design ensures
that the outputs will remain at a logic “Low” level.
Applications
DDR Memory Modules.
Provides complete DDR DIMM logic solution
with ASM5CVF857, ASM4SSTVF16857 and
ASM4SSTVF16859.
SSTL_2 compatible data registers.
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| ASM4SSTVF32852-114BT | DDR 24-Bit to 48-Bit Registered Buffer |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM4SSTVF32852-114BT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:DDR 24-Bit to 48-Bit Registered Buffer |
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