參數資料
型號: ASM4SSTVF32852-114BR
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: DDR 24-Bit to 48-Bit Registered Buffer
中文描述: SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA114
封裝: BGA-114
文件頁數: 8/13頁
文件大?。?/td> 105K
代理商: ASM4SSTVF32852-114BR
August
2004
ASM4SSTVF32852
rev 2.0
Timing Requirements
DDR 24-Bit to 48-Bit Registered Buffer
8 of 13
(Over recommended operating free-air temperature range, unless otherwise noted).
Switching Characteristics
(Over recommended operating free-air temperature range unless otherwise noted.)
V
DD
= 2.5 V ± 0.2 V
Symbol
From (input)
To (output)
Min
Typ
Max
Units
f
max
200
MHz
t
PD
CLK, CLKB
Q
1.9
2.7
ns
t
phl
RESETB
Q
4.5
ns
V
DD
= 2.5V±0.2V
Symbol
Parameters
Min
Max
Unit
f
CLOCK
Clock frequency
200
MHz
T
PD
Clock to output time
1.9
2.7
ns
T
RST
Reset to output time
4.5
ns
Setup time, fast slew rate
2,4
0.5
t
S
Setup time, slow slew rate
3,4
Data before CLK
, CLKB
0.7
ns
ns
Hold time, fast slew rate
2,4
0.3
t
h
Hold time, slow slew rate
3,4
Data after CLK
, CLKB
0.5
ns
ns
t
SL
Output slew rate
1
4
V/ns
Note:
1. Guaranteed by design, not 100% tested in production.
2. For data signal input slew rate >= 1V/ns
3. For data signal input slew rate >= 0.5 V/ns and < 1V/ns
4. CLK,CLKB signals input slew rates are >=1V/ns
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