參數(shù)資料
型號(hào)： ASC7611QS24
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： HARDWARE MONITOR WITH INTEGRATED FAN CONTROL
中文描述： 五金顯示器整合了風(fēng)扇控制
文件頁(yè)數(shù)： 9/40頁(yè)
文件大小： 505K
代理商： ASC7611QS24
P
P
- 9 -
Andigilog, Inc. 2006
www.andigilog.com
October 2006 - 70A05007
aSC7611
In this way, up to three aSC7611 devices can exists on a
SMBus at any time. Multiple aSC7611 devices can be
used to monitor additional processors in the temperature
zones. When using the non-default addresses, additional
circuitry will be required if Tach4 and PWM3 require to
function correctly. Such circuitry could consist of GPIO
pins from a micro-controller. During the first
communication the micro-controller would drive the
AddressEnable
and Address Select pins to the proper
state for the required address. After the first SMBus
communication the micro-controller would drive its pins into
Tri-State allowing TACH4 and PWM3 to operate correctly.
Writing to and Reading from the aSC7611
All read and write operations must begin with a start
condition generated by the master device. After the start
condition, the master device must immediately send a
slave address (7-bits) followed by a R/
W
bit. If the slave
address matches the address of the aSC7611, it sends an
ACK by pulling the SDA line low for one clock. Read or
write operations may contain one- or two-bytes. See
Figures 2 through 6 for timing diagrams for all aSC7611
operations.
Setting the Register Address Pointer
For all operations, the address pointer stored in the
address pointer register must be pointing to the register
address that is going to be written to or read from. This
register’s content is automatically set to the value of the
first byte following the R/
W
bit being set to 0.
After the aSC7611 sends an ACK in response to receiving
the address and R/
W
bit, the master device must transmit
an appropriate 8-bit address pointer value as explained in
the Registers section of this data sheet. The aSC7611 will
send an ACK after receiving the new pointer data.
The register address pointer set operation is illustrated in
Figure 2. If the address pointer is not a valid address the
aSC7611 will internally terminate the operation. Also recall
that the address register retains the current address pointer
value between operations. Therefore, once a register is
being pointed to, subsequent read operations do not
require another Address Pointer set cycle.
Writing to Registers
All writes must start with a pointer set as described
previously, even if the pointer is already pointing to the
desired register. The sequence is described in Figure 2.
Immediately following the pointer set, the master must
begin transmitting the data to be written. After transmitting
each byte of data, the master must release the SDA line for
one clock to allow the aSC7611 to acknowledge receiving
the byte. The write operation should be terminated by a
stop condition from the master.
Reading from Registers
To read from a register other than the one currently being
pointed to by the address pointer register, a pointer set
sequence to the desired register must be done as
described previously. Immediately following the pointer
set, the master must perform a repeat start condition that
indicates to the aSC7611 that a read is about to occur. It is
important to note that if the repeat start condition does not
occur, the aSC7611 will assume that a write is taking place,
and the selected register will be overwritten by the
upcoming data on the data bus. The read sequence is
described in Figure 4. After the start condition, the master
must again send the device address and read/write bit.
This time the R/
W
bit must be set to 1 to indicate a read.
The rest of the read cycle is the same as described in the
previous paragraph for reading from a preset pointer
location.
If the pointer is already pointing to the desired register, the
master can read from that register by setting the R/
W
bit
(following the slave address) to a 1. After sending an ACK,
the aSC7611 will begin transmitting data during the
following clock cycle. After receiving the 8 data bits, the
master device should respond with a NACK followed by a
stop condition.
If the master is reset while the aSC7611 is in the process of
being read, the master should perform an SMBus reset.
This is done by holding the data or clock low for more than
35ms, allowing all SMBus devices to be reset. This follows
the SMBus 2.0 specification of 25-35ms.
When the aSC7611 detects an SMBus reset, it will prepare
to accept a new start sequence and resume
communication from a known state.
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