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參數(shù)資料
| 型號： | ASC7611QS24 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HARDWARE MONITOR WITH INTEGRATED FAN CONTROL |
| 中文描述： | 五金顯示器整合了風(fēng)扇控制 |
| 文件頁數(shù)： | 19/40頁 |
| 文件大?。?/td> | 505K |
| 代理商： | ASC7611QS24 |
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Andigilog, Inc. 2006
www.andigilog.com
October 2006 - 70A05007
aSC7611
Register
Address
Read/
Write
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
2Dh
R
Tach 3 MS Byte
15
14
13
12
11
10
9
8
N/A
2Eh
2Fh
R
R
Tach 4 LS Byte
Tach 4 MS Byte
7
15
6
14
5
13
4
12
3
11
2
10
1
9
0
8
N/A
The Fan Tachometer Reading registers contains the number of 11.111
μ
s periods (90 kHz) between full fan revolutions. The
results are based on the time interval of two tachometer pulses, since most fans produce two tachometer pulses per full
revolution. These registers will be updated at least once every second. Common interpretation of tachometer readings is to
take the binary period measurement and convert it to RPM. This may be done by applying the formula:
RPM = (90,000 x 60)/(Decimal Equivalent of binary Tach Reading)
The value, for each fan, is represented by a 16-bit unsigned number.
The Fan Tachometer Reading registers will always return an accurate fan tachometer measurement, even when a fan is
disabled or non-functional, however, if PWM commands for a fan (register 30h to 32h) is zero, tach measurements are
suspended and the last reading may remain in the register.
FF FFh indicates that the fan is not spinning, or that the tachometer input is not connected to a valid signal. This value may
be FF FEh or FF FCh if Measurement Duration, bits 1:0 of register 3A-3Dh are set to 01 or 00, respectively. These registers
are read-only – a write to these registers has no effect.
When the LSByte of the aSC7611 16-bit register is read, the other byte (MSByte) is latched at the current value until it is
read. At the end of the MSByte read the Fan Tachometer Reading registers are updated. During spin-up, the PWM duty
cycle reported is 0%.
Registers 54-5Bh: Fan Tachometer Limits
Register
Address
Read/
Write
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
54h
R/W
Tach 1 Minimum
LS Byte
7
6
5
4
3
2
1
0
FF
55h
R/W
Tach 1 Minimum
MS Byte
15
14
13
12
11
10
9
8
FF
56h
R/W
Tach 2 Minimum
LS Byte
7
6
5
4
3
2
1
0
FF
57h
R/W
Tach 2 Minimum
MS Byte
15
14
13
12
11
10
9
8
FF
58h
R/W
Tach 3 Minimum
LS Byte
Tach 3 Minimum
MS Byte
7
6
5
4
3
2
1
0
FF
59h
R/W
15
14
13
12
11
10
9
8
FF
5Ah
R/W
Tach 4 Minimum
LS Byte
7
6
5
4
3
2
1
0
FF
5Bh
R/W
Tach 4 Minimum
MS Byte
15
14
13
12
11
10
9
8
FF
The Fan Tachometer Low Limit registers indicate the tachometer reading under which the corresponding bit will be set in the
Interrupt Status Register 2 register. In Auto Fan Control mode, the fan can run at low speeds, so care should be taken in
software to ensure that the limit is high enough not to cause sporadic alerts. The fan tachometer will not cause a bit to be
set in Interrupt Status Register 2 if the current value in Current PWM Duty registers (30h to 32h) is 00h or if the fan is
disabled via the Fan Configuration Register. Interrupts will not be generated for a fan if its minimum is set to FF FFh except
for timeout. Setting the Ready/Lock/Start/Override register Lock bit has no effect on these registers.
Given the relative insignificance of Bit 0 and Bit 1, these bits could be programmed to designate the physical location of the
fan generating the tachometer signal, as follows:
Register Name
Bit 1
Bit 0 (LSB)
CPU Cooler
0
0
Memory Controller
0
1
Chassis Front
1
0
Chassis Rear
1
1
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