參數(shù)資料
型號(hào)： AS9C25512M2018L
廠商： Alliance Semiconductor Corporation
英文描述： 2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
中文描述： 2.5V的512/256K × 18同步雙與3.3V或2.5V接口端口靜態(tài)存儲(chǔ)器
文件頁(yè)數(shù)： 13/30頁(yè)
文件大?。?/td> 1100K
代理商： AS9C25512M2018L
AS9C25512M2018L
AS9C25256M2018L
9/24/04, v.1.2
Alliance Semiconductor
P. 13 of 30
Timing waveform of read cycle
[7]
Notes:
1. Both Flow-through and Pipeline Outputs indicated. A particular port is configured in Flow-through mode if PL/FT for that port is driven low,
and in Pipeline mode if PL/FT is driven high or left unconnected.
2. Parameters t
CYC
, t
CH
and t
CL
are different in Flow-through and Pipeline modes of operation (Refer AC Timing characteristics).
3. CE is an internal signal.CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H).
Timings indicated for CE hold good for CE0 and CE1
4. BEn refers to any one of the 2 byte controls [n = 1 or 0] and DATA OUT refers to the corresponding Byte.
5. Counter set in “Load” mode (ADS = L,INC = X,RPT = H).
6. OE is an asynchronous input.
7. All timings are similar for both ports.
8. Read with Byte disabled. Data is not read out.Bus in High-Z condition.
CLK
CE
[3]
ADDRESS
[5]
OE
[6]
BEn
[4]
R/W
[Pipeline Mode]
t
CEH
t
CES
Q1
A1
A2
t
CYC
[2]
t
CL
t
CH
t
AS
t
AH
t
BS
t
BH
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
Q10
Read
(A1)
t
CDP
t
OHP
t
HZCP
t
LZCP
t
HZOE
t
LZOE
DATA OUT
[1]
Q2
Q8
Read
(A2)
Dsel
Read
[8]
(A4)
Dsel
Read
(A6)
Read
(A7)
Read
(A8)
Dsel
Read
(A10)
Dsel
Read
(A12)
Don’t care
Undefined
t
OE
t
WS
t
WH
t
LZOE
Q6
[Pipeline Mode]
Q1
Q10
t
CDF
t
OHF
t
HZCF
t
LZCF
t
HZOE
t
LZOE
Q2
Q8
t
OE
t
LZOE
Q6
OE
[6]
[Flow-through Mode]
[Flow-through Mode]
DATA OUT
[1]
Q12
相關(guān)PDF資料
PDF描述
AS9C25512M2018L-200TI 2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25512M2018L-250BC 2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25512M2018L-250BI 2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25512M2018L-250FC 2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25512M2018L-250FI 2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS9C25512M2018L-133BC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25512M2018L-133BI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25512M2018L-133FC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25512M2018L-133FI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25512M2018L-133TC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
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