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參數資料
| 型號： | AS9C25512M2018L |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| 中文描述： | 2.5V的512/256K × 18同步雙與3.3V或2.5V接口端口靜態(tài)存儲器 |
| 文件頁數： | 1/30頁 |
| 文件大?。?/td> | 1100K |
| 代理商： | AS9C25512M2018L |
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September 2004
Preliminary Information
Copyright Alliance Semiconductor. All rights reserved.
AS9C25512M2018L
AS9C25256M2018L
2.5V 512/256K X 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
9/24/04; v.1.2
Alliance Semiconductor
P. 1 of 30
Features
True Dual-Port memory cells that allow simulta-
neous access of the same memory location
Organisation: 524,288/262,144 × 18
[1]
Fully Synchronous, independent operation on
both ports
Selectable Pipeline or Flow-Through output
mode
Fast clock speeds in Pipeline output mode: 250
MHz operation (9Gbps bandwidth)
Fast clock to data access: 2.8ns for Pipeline out-
put mode
Asynchronous output enable control
Fast OE access times: 2.8ns
Double Cycle Deselect (DCD) for Pipeline Out-
put Mode
19/18
[1]
-bit counter with Increment, Hold and
Repeat features on each port
Dual Chip enables on both ports for easy
depth expansion
Interrupt and Collision Detection Features
2.5 V power supply for the core
LVTTL compatible, selectable 3.3V or
2.5V power supply for I/Os, addresses,
clock and control signals on each port
Snooze modes for each port for standby
operation
15mA typical standby current in power
down mode
Available in 256-pin Ball Grid Array
(BGA), 144-pin Thin Quad Flatpack
(TQFP) and 208-pin fine pitch Ball Grid
Array (fpBGA)
Supports JTAG features compliant with
IEEE 1149.1
Selection guide
Feature
-250
4
250
2.8
150
6.5
TBD
18
-200
5
200
3.4
133
7.5
350
18
-166
6
166
3.6
100
10
300
18
-133
7.5
133
4.2
83
12
260
18
Units
ns
MHz
ns
MHz
ns
mA
mA
Minimum cycle time
Maximum Pipeline clock frequency
Maximum Pipeline clock access time
Maximum flow-through clock frequency
Maximum flow-through clock access time
Maximum operating current
Maximum snooze mode current
Note:
1. AS9C25512M2018L/AS9C25256M2018L
相關PDF資料 |
PDF描述 |
|---|---|
| AS9C25512M2018L-200TI | 2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| AS9C25512M2018L-250BC | 2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| AS9C25512M2018L-250BI | 2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| AS9C25512M2018L-250FC | 2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| AS9C25512M2018L-250FI | 2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AS9C25512M2018L-133BC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| AS9C25512M2018L-133BI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| AS9C25512M2018L-133FC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| AS9C25512M2018L-133FI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| AS9C25512M2018L-133TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
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