參數(shù)資料
型號: AS8202
廠商: AUSTRIAMICROSYSTEMS AG
元件分類: 微控制器/微處理器
英文描述: TTP/C-C2 Communication Controller
中文描述: 2 CHANNEL(S), 25M bps, SERIAL COMM CONTROLLER, PQFP80
封裝: PLASTIC, TQFP-80
文件頁數(shù): 4/10頁
文件大?。?/td> 101K
代理商: AS8202
TTP/C-C2 Communication Controller
– Preliminary Data Sheet
AS8202
Rev. 1.0, October 2000
Page 4 of 4
Pin Description
Pin
1,12,21,32,51,61,71
4,13,24,33,43,52,62,72
2
Name
Vdd
Vss
xout0
Dir
P
P
O
Description
positive power supply
Negative power supply
Main clock: analog pad from oscillator / leave open
when providing external clock
Main clock: analog pad from oscillator / use as input
when providing external clock
Transmit data channel 0
Transmit enable channel 0
TTP/C synchronous: Transmit clock channel 0
TTP/C synchronous: Receive error channel 0
TTP/C synchronous: Receive clock channel 0
TTP/C synchronous: Receive data valid channel 0
Receive data channel 0
Transmit data channel 1
Transmit enable channel 1
TTP/C synchronous: Transmit clock channel 1
TTP/C synchronous: Receive error channel 1
TTP/C synchronous: Receive clock channel 1
TTP/C synchronous: Receive data valid channel 1
Receive data channel 1
Bus guardian clock: analog pad from oscillator / leave
open when providing external clock
Bus guardian clock: analog pad from oscillator / use as
input when providing external clock
Test input, connect to Vss
Test input, connect to Vss
PLL disable pin
Test input, connect to Vss
Test input, connect to Vss
main reset input signal, active low
CNI control signal, CNI time signal
Configurable: either generic output port (f.e. to drive
LEDs) or timing signal TIME_TICK
Configurable: either generic output port (f.e. to drive
LEDs) or timing signal TIME_OVERFLOW
Configurable: either generic output port (f.e. to drive
LEDs) or timing signal TIME_OVERFLOW
Test input, connect to Vss
Host interface (CNI) address bus
Host interface (CNI) data bus, tristate
Host interface (CNI) chip enable, active low
Host interface (CNI) output enable, active low
Host interface (CNI) write enable, active low
Host interface (CNI) transfer finish signal, active low
Connect to Vss
Connect to Vdd
Do not connect
Do not connect
3
xin0
I
5
6
7
8
9
10
11
14
15
16
17
18
19
20
22
txd[0]
cts[0]
txclk[0]
rxer[0]
rxclk[0]
rxdv[0]
rxd[0]
txd[1]
cts[1]
txclk[1]
rxer[1]
rxclk[1]
rxdv[1]
rxd[1]
xout1
O
PU
O
PD
I
PD
I
PU
I
PD
I
PU
I
PU
O
PU
O
PD
I
PD
I
PU
I
PD
I
PU
I
PU
O
23
xin1
I
25
26
27
28
29
30
31
34
test_se
stest
plloff
ftest
fidis
resetb
time_signalb
led[0]/microtick
I
PD
I
PD
I
PD
I
PD
I
PD
I
O
PU
O
PD
35
led[1]/time_tick
O
PD
36
led[2]/time_overflow
O
PD
37
38-42,44-50
53-60,63-70
73
74
75
76
77
78
79
80
I
I
PD
Input CMOS with pull down
O
PD
Output with pull down when tristate
I/O Input/Output CMOS tristate
mtest
ram_address[0:11]
ram_data[0:15]
ram_ceb
ram_oeb
ram_web
ram_readyb
to Vss
to Vdd
high Z
high Z
I
PD
I
I/O
I
PU
I
PU
I
PU
O
PU
P
I
PU
Input CMOS
I
PU
O
O
PU
P
Input CMOS with pull up
Output CMOS
Output with pull up when tristate
Power Pin
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