參數(shù)資料
型號(hào)： AS80196CB
廠商： Intel Corp.
英文描述： ADVANCED 16-BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2.0
中文描述： 先進(jìn)的16位單片機(jī)CHMOS集成CAN 2.0
文件頁數(shù)： 7/33頁
文件大?。?/td> 453K
代理商： AS80196CB
87C196CA/87C196CB
Symbol
Name and Function
V
CC
Main Supply Voltage (
a
5V).
V
SS
,V
SS1
Digital circuit ground (0V). There are 7 V
SS
pins CB (4 on CA), all of which MUST be
connected to a single ground plane.
V
REF
Reference for the A/D converter (
a
5V). V
REF
is also the supply voltage to the analog
portion of the A/D converter and the logic used to read Port 0. Must be connected for
A/D and Port 0 to function.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same potential
as V
SS
.
Programming voltage for EPROM parts. It should be
a
12.5V for programming. It is
also the timing pin for the return from powerdown circuit. Connect this pin with a 1
m
F
capacitor to V
SS
and a 1Mohm resistor to V
CC
. If this function is not used, V
PP
may be
tied to V
CC
.
V
PP
XTAL1
Input of the oscillator inverter and the internal clock generator.
XTAL2
Output of the Oscillator Inverter.
RESET
Y
Reset input to the chip. Input low for at least 16 state times will reset the chip. The
subsequent low to high transition resynchronizes CLKOUT and commences a
10-state time sequence in which the PSW is cleared, bytes are read from 2018H,
201Ah and 201CH (if enabled) loading the CCB’s, and a jump to location 2080H is
executed. Input high for normal operation. RESET
Y
has an internal pullup.
NMI
A positive transition causes a non-maskable interrupt vector through memory location
203EH. If not used, this pin should be tied to V
SS
. May be used by Intel Evaluation
boards.
EA
Y
Input for memory select (External Access). EA
Y
equal to a high causes memory
accesses to locations 0FF2000H through 0FFFFFFH to be directed to on-chip
EPROM/ROM. EA
Y
equal to a low causes accesses to these locations to be directed
to off-chip memory. EA
Y
e a
12.5V causes execution to begin in the Programming
Mode. EA
Y
is latched at reset.
PLLEN
(196CB only)
Selects between PLL mode or PLL bypass mode. This pin must be either tied high or
low. PLLEN pin
e
0, bypass PLL mode. PLLEN pin
e
1, places a 4x PLL at the input
of the crystal oscillator. Allows for a low frequency crystal to drive the device (i.e.,
5 MHz
e
20 MHz operation).
P6.4–6.7/SSIO
Dual function I/O ports have a system function as Synchronous Serial I/O. Two pins
are clocks and two pins are data providing for full duplex capability. Also LSIO when
not used as SSIO.
P6.3/T1DIR
(CB only)
Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however, it
may also be used as a TIMER1 Direction input. The TIMER1 will increment when this
pin is high and decrements when this pin is low.
P6.2/T1CLK
(CB only)
Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however may
also be used as a TIMER1 Clock input. The TIMER1 will increment or decrement on
both positive and negative edges of this pin.
P6.0–6.1/EPA8–9
Dual function I/O port pins. Primary function is that of bidirectional I/O. System
function is that of High Speed capture and compare.
7
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