參數(shù)資料
型號: AS7C4098A
廠商: Alliance Semiconductor Corporation
英文描述: High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer with Address Latches 16-PDIP -55 to 125
中文描述: 2.5V的為512k × 32/36直通突發(fā)同步SRAM
文件頁數(shù): 6/19頁
文件大小: 524K
代理商: AS7C4098A
AS7C25512FT32A
AS7C25512FT36A
12/23/04, v. 1.2
Alliance Semiconductor
6 of 19
Write enable truth table (per byte)
Key:
X = don’t care, L = low, H = high, n = a, b, c, d;
BWE
,
BWn
= internal write signal.
Asynchronous Truth Table
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Function
GWE
BWE
BWa
BWb
BWc
BWd
Write All Bytes
L
X
X
X
X
X
H
L
L
L
L
L
Write Byte a
H
L
L
H
H
H
Write Byte c and d
H
L
H
H
L
L
Read
H
H
X
X
X
X
H
L
H
H
H
H
Operation
ZZ
H
L
L
L
L
OE
X
L
H
X
X
I/O Status
High-Z
Dout
High-Z
Din, High-Z
High-Z
Snooze mode
Read
Write
Deselected
Interleaved burst address (LBO = 1)
A1 A0
0 0
2
nd
Address
0 1
3
rd
Address
1 0
4
th
Address
1 1
Linear burst address (LBO = 0)
A1 A0
0 0
0 1
1 0
1 1
A1 A0
0 1
0 0
1 1
1 0
A1 A0
1 0
1 1
0 0
0 1
A1 A0
1 1
1 0
0 1
0 0
A1 A0
0 1
1 0
1 1
1 0
A1 A0
1 0
1 1
0 0
0 1
A1 A0
1 1
0 0
0 1
1 0
1
st
Address
1
st
Address
2
nd
Address
3
rd
Address
4
th
Address
相關(guān)PDF資料
PDF描述
AS7C25512FT36A-10TQIN 2.5V 512K x 32/36 flowthrough burst synchronous SRAM
AS7C25512FT36A-75TQC 2.5V 512K x 32/36 flowthrough burst synchronous SRAM
AS7C25512FT36A-75TQCN 2.5V 512K x 32/36 flowthrough burst synchronous SRAM
AS7C25512FT36A-75TQI 2.5V 512K x 32/36 flowthrough burst synchronous SRAM
AS7C25512FT36A-75TQIN 2.5V 512K x 32/36 flowthrough burst synchronous SRAM
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