參數(shù)資料
型號: AS7C3364PFS32A-150TQC
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 3.3V 64K X 32/36 pipeline burst synchronous SRAM
中文描述: 64K X 32 STANDARD SRAM, 10 ns, PQFP100
封裝: 14 X 20 MM, TQFP-100
文件頁數(shù): 6/11頁
文件大?。?/td> 235K
代理商: AS7C3364PFS32A-150TQC
AS7C3364PFS32A
AS7C3364PFS36A
2/1/01
Alliance Semiconductor
P. 6 of 11
Timing characteristics over operating range
*See “Notes” on page 10.
Key to switching waveforms
Parameter
Symbo
l
–166
–150
–133
–100
Unit
Notes
*
Min
Max
Min
Max
Min
Max
Min
Max
Clock frequency
f
Max
t
CYC
t
CYCF
t
CD
166
150
133
100
MHz
Cycle time (pipelined mode)
6
6.7
7.5
10
ns
Cycle time (flow-through mode)
10
10
12
12
ns
Clock access time (pipelined mode)
3.5
3.8
4.0
5.0
ns
Clock access time (flow-through
mode)
t
CDF
9
10
10
12
ns
Output enable LOW to data valid
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
AH
t
DH
t
WH
t
CSH
t
ADVS
t
ADSPS
t
ADSCS
t
ADVH
t
ADSPH
t
ADSCH
3.5
3.8
4.0
5.0
ns
Clock HIGH to output Low Z
0
0
0
0
ns
2,3,4
Data output invalid from clock HIGH
1.5
1.5
1.5
1.5
ns
2
Output enable LOW to output Low Z
0
0
0
0
ns
2,3,4
Output enable HIGH to output High Z
3.5
3.8
4.0
4.5
ns
2,3,4
Clock HIGH to output High Z
3.5
3.8
4.0
5.0
ns
2,3,4
Output enable HIGH to invalid output
0
0
0
0
ns
Clock HIGH pulse width
2.4
2.5
2.5
3.5
ns
5
Clock LOW pulse width
2.4
2.5
2.5
3.5
ns
5
Address setup to clock HIGH
1.5
1.5
1.5
2.0
ns
6
Data setup to clock HIGH
1.5
1.5
1.5
2.0
ns
6
Write setup to clock HIGH
1.5
1.5
1.5
2.0
ns
6,7
Chip select setup to clock HIGH
1.5
1.5
1.5
2.0
ns
6,8
Address hold from clock HIGH
0.5
0.5
0.5
0.5
ns
6
Data hold from clock HIGH
0.5
0.5
0.5
0.5
ns
6
Write hold from clock HIGH
0.5
0.5
0.5
0.5
ns
6,7
Chip select hold from clock HIGH
0.5
0.5
0.5
0.5
ns
6,8
ADV setup to clock HIGH
1.5
1.5
1.5
2.0
ns
6
ADSP setup to clock HIGH
1.5
1.5
1.5
2.0
ns
6
ADSC setup to clock HIGH
1.5
1.5
1.5
2.0
ns
6
ADV hold from clock HIGH
0.5
0.5
0.5
0.5
ns
6
ADSP hold fromclock HIGH
0.5
0.5
0.5
0.5
ns
6
ADSC hold from clock HIGH
0.5
0.5
0.5
0.5
ns
6
Undefined/don’t care
Falling input
Rising input
相關(guān)PDF資料
PDF描述
AS7C3364PFS32A-150TQI 3.3V 64K X 32/36 pipeline burst synchronous SRAM
AS7C3364PFS32A-166TQC 3.3V 64K X 32/36 pipeline burst synchronous SRAM
AS7C3364PFS32A-166TQI 3.3V 64K X 32/36 pipeline burst synchronous SRAM
AS7C3364PFS32A-100TQC 3.3V 64K X 32/36 pipeline burst synchronous SRAM
AS7C3364PFS32A-100TQI 3.3V 64K X 32/36 pipeline burst synchronous SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS7C3364PFS32A-150TQI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 64K X 32/36 pipeline burst synchronous SRAM
AS7C3364PFS32A-166TQC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 64K X 32/36 pipeline burst synchronous SRAM
AS7C3364PFS32A-166TQI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 64K X 32/36 pipeline burst synchronous SRAM
AS7C3364PFS32B 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 64K X 32/36 pipeline burst synchronous SRAM
AS7C3364PFS32B-133TQC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 64K X 32/36 pipeline burst synchronous SRAM