參數(shù)資料
型號(hào): AS7C3364PFS32A-150TQC
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 3.3V 64K X 32/36 pipeline burst synchronous SRAM
中文描述: 64K X 32 STANDARD SRAM, 10 ns, PQFP100
封裝: 14 X 20 MM, TQFP-100
文件頁數(shù): 3/11頁
文件大小: 235K
代理商: AS7C3364PFS32A-150TQC
AS7C3364PFS32A
AS7C3364PFS36A
2/1/01
Alliance Semiconductor
P. 3 of 11
Signal descriptions
Absolute maximum ratings
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.
Signal
CLK
A0–A15
DQ[a,b,c,d]
I/
O
I
I
I/O SYNC
Properties
CLOCK
SYNC
Description
Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.
Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
Address strobe processor. Asserted LOW to load a new bus address or to enter standby
mode.
Address strobe controller. Asserted LOW to load a new address or to enter standby mode.
Advance. Asserted LOW to continue burst read/write.
Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE and BW[a:d]
control write enable.
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs.
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a:d] are inactive the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
CE0
I
SYNC
CE1, CE2
I
SYNC
ADSP
I
SYNC
ADSC
ADV
I
I
SYNC
SYNC
GWE
I
SYNC
BWE
I
SYNC
BW[a,b,c,d] I
SYNC
OE
I
ASYNC
LBO
I
STATIC
default =
HIGH
Count mode. When driven High, count sequence follows Intel XOR convention. When
driven Low, count sequence follows linear convention.
This signal is internally pulled High.
18
FT
I
STATIC
Flow-through mode.When low, enables single register flow-through mode. Connect to V
DD
if unused or for pipelined operation.
Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
ZZ
I
ASYNC
Parameter
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
DC output current
Storage temperature (plastic)
Temperature under bias
Symbol
V
DD
, V
DDQ
V
IN
V
IN
P
D
I
OUT
T
stg
T
bias
Min
–0.5
–0.5
–0.5
–65
–65
Max
+4.6
V
DD
+ 0.5
V
DDQ
+ 0.5
1.8
50
+150
+135
Unit
V
V
V
W
mA
o
C
o
C
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS7C3364PFS32A-150TQI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 64K X 32/36 pipeline burst synchronous SRAM
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AS7C3364PFS32A-166TQI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 64K X 32/36 pipeline burst synchronous SRAM
AS7C3364PFS32B 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 64K X 32/36 pipeline burst synchronous SRAM
AS7C3364PFS32B-133TQC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 64K X 32/36 pipeline burst synchronous SRAM