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參數(shù)資料
| 型號： | AS7C33256FT18B-80TQI |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 256K x 18 Flow Through Synchronous SRAM |
| 中文描述： | 256K X 18 STANDARD SRAM, 8 ns, PQFP100 |
| 封裝： | 14 X 20 MM, TQFP-100 |
| 文件頁數(shù)： | 10/19頁 |
| 文件大小： | 401K |
| 代理商： | AS7C33256FT18B-80TQI |
AS7C33256FT18B
12/10/04; v.1.4
Alliance Semiconductor
P. 10 of 19
Snooze Mode Electrical Characteristics
Timing characteristics over operating range
Parameter
Sym
t
CYC
t
CD
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
AH
t
DH
t
WH
t
CSH
t
ADVS
t
ADSPS
t
ADSCS
t
ADVH
t
ADSPH
t
ADSCH
–65
-75
-80
–10
Unit
ns
Notes
1
1
See “Notes” on page 16.
Min Max
7.5
Min
8.5
Max
–
Min
10
Max
–
Min
12
Max
–
Cycle time
–
Clock access time
–
6.5
–
7.5
–
8.0
–
10
ns
Output enable LOW to data valid
–
3.5
–
3.5
–
4.0
–
4.0
ns
Clock HIGH to output Low Z
2.5
–
2.5
–
2.5
–
2.5
–
ns
2,3,4
Data output invalid from clock HIGH
2.5
–
2.5
–
2.5
–
2.5
–
ns
2
Output enable LOW to output Low Z
0
–
0
–
0
–
0
–
ns
2,3,4
Output enable HIGH to output High Z
–
3.0
–
3.5
–
4.0
–
5.0
ns
2,3,4
Clock HIGH to output High Z
–
3.0
–
3.5
–
4.0
–
5.0
ns
2,3,4
Output enable HIGH to invalid output
0
–
0
–
0
–
0
–
ns
Clock HIGH pulse width
2.5
–
3.0
–
4.0
–
4.0
–
ns
5
Clock LOW pulse width
2.5
–
3.0
–
4.0
–
4.0
–
ns
5
Address setup to clock HIGH
1.5
–
2.0
–
2.0
–
2.0
–
ns
6
Data setup to clock HIGH
1.5
–
2.0
–
2.0
–
2.0
–
ns
6
Write setup to clock HIGH
1.5
–
2.0
–
2.0
–
2.0
–
ns
6,7
Chip select setup to clock HIGH
1.5
–
2.0
–
2.0
–
2.0
–
ns
6,8
Address hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Data hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Write hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,7
Chip select hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,8
ADV setup to clock HIGH
1.5
–
2.0
–
2.0
–
2.0
–
ns
6
ADSP setup to clock HIGH
1.5
–
2.0
–
2.0
–
2.0
–
ns
6
ADSC setup to clock HIGH
1.5
–
2.0
–
2.0
–
2.0
–
ns
6
ADV hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
ADSP hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
ADSC hold from clock HIGH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Description
Conditions
ZZ > V
IH
Symbol
I
SB2
t
PDS
t
PUS
t
ZZI
t
RZZI
Min
Max
30
Units
mA
cycle
cycle
cycle
Current during Snooze Mode
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
2
2
2
0
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