參數(shù)資料
型號: AS7C252MPFS18A-200TQIN
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 2.5V 2M x 18 pipelined burst synchronous SRAM
中文描述: 2M X 18 STANDARD SRAM, 3.1 ns, PQFP100
封裝: 14 X 20 MM, LEAD FREE, TQFP-100
文件頁數(shù): 6/18頁
文件大小: 507K
代理商: AS7C252MPFS18A-200TQIN
AS7C252MPFS18A
2/14/05,
v.1.3
Alliance Semiconductor
6 of 18
Write enable truth table (per byte)
Key:
X = don’t care, L = low, H = high, n = a, b;
BWE
,
BWn
= internal write signal.
Asynchronous Truth Table
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Function
GWE
L
H
H
H
H
H
BWE
X
L
L
L
H
L
BWa
X
L
L
H
X
H
BWb
X
L
H
L
X
H
Write All Bytes
Write Byte a
Write Byte b
Read
Operation
ZZ
H
L
L
L
L
OE
X
L
H
X
X
I/O Status
High-Z
Dout
High-Z
Din, High-Z
High-Z
Snooze mode
Read
Write
Deselected
Interleaved burst address (LBO = 1)
A1 A0
Starting Address
First Increment
Second Increment
Third Increment
Linear burst address (LBO = 0)
A1 A0
Starting Address
First Increment
Second Increment
Third Increment
A1 A0
0 1
0 0
1 1
1 0
A1 A0
1 0
1 1
0 0
0 1
A1 A0
1 1
1 0
0 1
0 0
A1 A0
0 1
1 0
1 1
1 0
A1 A0
1 0
1 1
0 0
0 1
A1 A0
1 1
0 0
0 1
1 0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
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