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參數(shù)資料
| 型號： | AS7C252MPFS18A-200TQIN |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2.5V 2M x 18 pipelined burst synchronous SRAM |
| 中文描述： | 2M X 18 STANDARD SRAM, 3.1 ns, PQFP100 |
| 封裝： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大小： | 507K |
| 代理商： | AS7C252MPFS18A-200TQIN |
February 2005
Copyright Alliance Semiconductor. All rights reserved.
AS7C252MPFS18A
2/14/05, v.1.3
Alliance Semiconductor
1 of 18
2.5V 2M
×
18 pipelined burst synchronous SRAM
Features
Organization: 2,097,152 words × 18 bits
Fast clock speeds to 200 MHz
Fast clock to data access:
3.1/3.5/3.8 ns
Fast OE access time: 3.1/3.5/3.8 ns
Fully synchronous register-to-register operation
Single-cycle deselect
Asynchronous output enable control
Available in 100-pin TQFP package
Individual byte write and global write
Multiple chip enables for easy expansion
2.5V core power supply
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Logic block diagram
Selection guide
-200
5
200
3.1
450
170
90
-166
6
166
3.5
400
150
90
-133
7.5
133
3.8
350
140
90
Units
ns
MHz
ns
mA
mA
mA
Minimum cycle time
Maximum clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
Burst logic
ADSC
ADSP
ADV
LBO
CLK
CS
CLR
21
19
21
A[20:0]
21
Address
register
D
CS
Q
CLK
2M x 18
Memory
array
18
18
DQb
CLK
D
Byte Write
D
registers
Q
DQa
CLK
Q
Enable
register
CE
CLK
D
Q
Enable
rdelay
CLK
D
Q
Output
registers
CLK
Input
registers
Power
down
DQ[a,b]
2
CE0
CE2
BW
b
BW
a
OE
ZZ
OE
CLK
BWE
GWE
18
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