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參數(shù)資料
| 型號： | AS7C1028 |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 5V 256K X 4 CMOS SRAM (Common I/O) |
| 中文描述： | 5V的256K × 4 CMOS SRAM的（通用的I / O） |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 128K |
| 代理商： | AS7C1028 |
AS7C1028
12/5/06;
V.1.0
Alliance Memory
P. 6 of 8
AC test conditions
- Output load: see Figure B or Figure C.
- Input pulse level: GND to
V
CC
. See Figure A.
- Input rise and fall times: 3 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
Notes:
1
2
3
4
5
6
7
8
9
10
CE
or
WE
must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11
All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 C=30pF, except on High Z and Low Z parameters, where C=5pF.
During V
CC
power-up, a pull-up resistor to V
CC
on
CE
is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions
, Figures A, B, C.
These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured
±
200mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE
is High for read cycle.
CE
and
OE
are Low for read cycle.
Address valid prior to or coincident with
CE
transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
350
Ω
C(13)
320
Ω
D
out
GND
V
CC
168
Ω
D
out
+1.72V (5V)
Figure C: Output load
255
Ω
C(13)
480
Ω
D
out
GND
+5V
Figure B: Output lo
ad
Thevenin equivalent
10%
90%
10%
90%
GND
V
CC
Figure A: Input pulse
3 ns
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