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參數(shù)資料
| 型號： | AS7C1028 |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 5V 256K X 4 CMOS SRAM (Common I/O) |
| 中文描述： | 5V的256K × 4 CMOS SRAM的（通用的I / O） |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 128K |
| 代理商： | AS7C1028 |
AS7C1028
12/5/06;
V.1.0
Alliance Memory
P. 2 of 8
Functional description
The AS7C1028 is a 5V
high-performance C
MOS 1,048,576-bit Static Random-Access Memory (SRAM) device organized
as 262,144 words × 4 bits. It is designed for memory applications requiring fast data access at low voltage, including
Pentium
TM
, PowerPC
TM
, and portable computing. Alliance’s advanced circuit design and process techniques permit 5.0V
operation without sacrificing performance or operating margins.
The device enters
standby mode
when
CE
is high. Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 12 ns with output
enable access times (t
OE
) of 6 ns are ideal for high-performance applications. The chip enable (
CE
) input permits easy memory
expansion with multiple-bank memory organizations.
A write cycle is accomplished by asserting chip enable (
CE
) and write enable (
WE
) LOW. Data on the input pins I/O0-I/O7 is
written on the rising edge of
WE
(write cycle 1) or
CE
(write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (
OE
) or write enable (
WE
).
A read cycle is accomplished by asserting chip enable (
CE
) and output enable (
OE
) LOW, with write enable (
WE
) high. The
chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write
enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0±0.5V supply. The AS7C1028 is packaged in
high volume industry standard packages.
Absolute maximum ratings
Parameter
Symbol
Voltage on V
CC
relative to GND
V
t1
Voltage on any pin relative to GND
V
t2
Power dissipation
P
D
Storage temperature (plastic)
T
stg
Ambient temperature with V
CC
applied
T
bias
DC current into outputs (low)
I
OUT
Note:
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Notes:
H = V
IH
,
L = V
IL
, x = Don’t care.
V
LC
= 0.2V, V
HC
= V
CC
- 0.2V.
Other inputs
≥
V
HC
or V
LC
.
Min
–0.5
–0.5
–
–55
–55
–
Max
+7.0
V
CC
+ 0.5
1.25
+125
+125
50
Unit
V
V
W
o
C
o
C
mA
CE
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
Data
High Z
High Z
D
OUT
D
IN
Mode
Standby (I
SB
, I
SB1
)
Output disable (I
CC
)
Read (I
CC
)
Write (I
CC
)
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|---|---|
| AS7C1029 | 5V 256K X 4 CMOS SRAM (Center power and ground) |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AS7C1028-12JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| AS7C1028-12PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| AS7C1028-12TJC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| AS7C1028-15JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| AS7C1028-15PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
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