- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381315 > AS7C1026B (Alliance Semiconductor Corporation) 5 V 64K X 16 CMOS SRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | AS7C1026B |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 5 V 64K X 16 CMOS SRAM |
| 中文描述： | 5伏64K的× 16 CMOS SRAM的 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 122K |
| 代理商： | AS7C1026B |
AS7C1026B
3/26/04, v 1.3
Alliance Semiconductor
P. 7 of 10
AC test conditions
– Output load: see Figure B.
– Input pulse level: GND to 3.5 V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5
Notes
1
2
3
4
5
6
7
8
9
10 N/A.
11
All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions
, Figures A and B.
These parameters are specified with C
L
= 5 pF, as in Figures B. Transition is measured ± 500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is high for read cycle.
CE and OE are low for read cycle.
Address is valid prior to or coincident with CE transition low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
168
Thevenin Equivalent:
D
OUT
+1.728 V
255
C
13
480
GND
+5 V
Figure B: 5 V Output load
10%
90%
10%
90%
GND
+3.5V
Figure A: Input pulse
2 ns
D
OUT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C1026B-12TIN | 5 V 64K X 16 CMOS SRAM |
| AS7C1026B-15JC | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 |
| AS7C1026B-15JCN | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 |
| AS7C1026B-15JI | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 |
| AS7C1026B-15TC | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C1026B-10JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5 V 64K X 16 CMOS SRAM |
| AS7C1026B-10JCN | 制造商:Alliance Memory Inc 功能描述:64K X 16 STANDARD SRAM, 10 NS |
| AS7C1026B-10JI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5 V 64K X 16 CMOS SRAM |
| AS7C1026B-10JIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5 V 64K X 16 CMOS SRAM |
| AS7C1026B-10TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5 V 64K X 16 CMOS SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。