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參數(shù)資料
| 型號： | AS7C1026B |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 5 V 64K X 16 CMOS SRAM |
| 中文描述： | 5伏64K的× 16 CMOS SRAM的 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 122K |
| 代理商： | AS7C1026B |
March 2004
Copyright Alliance Semiconductor. All rights reserved.
AS7C1026B
5 V 64K X 16 CMOS SRAM
3/26/04, v 1.3
Alliance Semiconductor
P. 1 of 10
Features
Industrial and commercial versions
Organization: 65,536 words × 16 bits
Center power and ground pins for low noise
High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
Low power consumption: ACTIVE
- 605 mW / max @ 10 ns
Low power consumption: STANDBY
- 55 mW / max CMOS I/O
6 T 0.18 u CMOS technology
Easy memory expansion with
CE
,
OE
inputs
TTL-compatible, three-state I/O
JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
ESD protection
≥
2000 volts
Latch-up current
≥
200 mA
Logic block diagram
64 K × 16
Array
OE
LB
CE
WE
Column decoder
R
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A
A
A
A
A
A
A
A
Control circuit
I/O0–I/O7
I/O8–I/O15
UB
I/O
buffer
Pin arrangement
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
I/O13
I/O12
GND
V
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
A0
CE
I/O0
I/O1
I/O2
I/O3
V
CC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
44-Pin SOJ (400 mil), TSOP 2
UB
LB
I/O15
I/O14
2
3
4
A3
A2
A1
1
A4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A6
A7
OE
A5
A
Selection guide
-10
10
5
110
10
-12
12
6
100
10
-15
15
7
90
10
-20
20
8
80
10
Unit
ns
ns
mA
mA
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C1026B-12TIN | 5 V 64K X 16 CMOS SRAM |
| AS7C1026B-15JC | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 |
| AS7C1026B-15JCN | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 |
| AS7C1026B-15JI | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 |
| AS7C1026B-15TC | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C1026B-10JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5 V 64K X 16 CMOS SRAM |
| AS7C1026B-10JCN | 制造商:Alliance Memory Inc 功能描述:64K X 16 STANDARD SRAM, 10 NS |
| AS7C1026B-10JI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5 V 64K X 16 CMOS SRAM |
| AS7C1026B-10JIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5 V 64K X 16 CMOS SRAM |
| AS7C1026B-10TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5 V 64K X 16 CMOS SRAM |
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