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參數(shù)資料
| 型號(hào)： | AS7C1025B-15TJI |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 |
| 中文描述： | 128K X 8 STANDARD SRAM, 15 ns, PDSO32 |
| 封裝： | 0.300 INCH, SOJ-32 |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大小： | 103K |
| 代理商： | AS7C1025B-15TJI |
AS7C1025B
3/26/04, v. 1.3
Alliance Semiconductor
P. 7 of 9
Package dimensions
e
D
E1
Pin 1
b
B
A1
A2
c
E
Seating
plane
E2
A
32-pin SOJ
300 mil/400 mil
Symbol
A
A1
A2
B
b
c
D
E
E1
E2
e
32-pin SOJ
300 mil
Min
0.128
0.025
0.095
0.026
0.016
0.007
0.820
0.255
0.295
0.330
0.050 BSC
32-pin SOJ
400 mil
Min
0.132
0.025
0.105
0.026
0.015
0.007
0.820
0.354
0.395
0.435
0.050 BSC
Max
0.145
-
0.105
0.032
0.020
0.010
0.830
0.275
0.305
0.340
Max
0.146
-
0.115
0.032
0.020
0.013
0.830
0.378
0.405
0.445
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C1025B-20JC | 5V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C1025B-20JCN | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 |
| AS7C1025B-20JI | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 |
| AS7C1025B-20TJI | 5V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C1025B-10TJC | 128 x 64 pixel format, LED or EL Backlight available |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C1025B-15TJIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C1025B-20JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C1025B-20JCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C1025B-20JI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C1025B-20JIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM (Center power and ground) |
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