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參數(shù)資料
| 型號： | AS7C1025B-15TJI |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 |
| 中文描述： | 128K X 8 STANDARD SRAM, 15 ns, PDSO32 |
| 封裝： | 0.300 INCH, SOJ-32 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 103K |
| 代理商： | AS7C1025B-15TJI |
AS7C1025B
3/26/04, v. 1.3
Alliance Semiconductor
P. 6 of 9
Write waveform 2 (CE controlled)
10,11
AC test conditions
– Output load: see Figure B.
– Input pulse level: GND to 3.5 V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5 V.
Notes
1
2
3
4
5
6
7
8
9
10 N/A
11
12 N/A.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
During V
CC
power-up, a pull-up resistor to V
CC
on
CE
is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions
, Figures A and B.
t
CLZ
and t
CHZ
are specified with CL = 5 pF, as in Figure B. Transition is measured
±
500 mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE
is high for read cycle.
CE
and
OE
are low for read cycle.
Address is valid prior to or coincident with
CE
transition low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
t
AW
Address
CE
WE
D
OUT
t
CW
t
WP
t
DW
Data valid
t
DH
t
AH
t
WR
t
WZ
t
WC
t
AS
D
IN
168
Thevenin equivalent:
D
OUT
+1.728 V
255
C
13
480
D
OUT
GND
+5 V
Figure B: 5 V Output load
10%
90%
10%
90%
GND
+3.5 V
Figure A: Input pulse
2 ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C1025B-20JC | 5V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C1025B-20JCN | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 |
| AS7C1025B-20JI | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 |
| AS7C1025B-20TJI | 5V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C1025B-10TJC | 128 x 64 pixel format, LED or EL Backlight available |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C1025B-15TJIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C1025B-20JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C1025B-20JCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C1025B-20JI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C1025B-20JIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 128K X 8 CMOS SRAM (Center power and ground) |
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