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參數(shù)資料
| 型號： | AS5502 |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | 調(diào)制器/解調(diào)器 |
| 英文描述： | Multimode Powerline-Modem |
| 中文描述： | 2.4 kbps DATA, MODEM, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 5/26頁 |
| 文件大?。?/td> | 315K |
| 代理商： | AS5502 |
1.1 SERIF, RESET, TIMING
SERIAL INTERFACE
SD-OUT
SD-IN
SCLK
A0/CS
Control Register Output
POR
BAND GAP REF.
TIMING
VREF
RESN
RES-TH
MCLK
CKSYS
Test1,2
SC-CLK
Fmixer
Mclk/2
mux
CONTROL REGISTERS
Default Setting Rom
TXEN
ZC
BD1,2, ZCEN, MMV
TXENI
CKTX
IF-SCCLK
1.1.1 SERIAL INTERFACE
There is a serial interface implemented for setting the control bits by a CPU.
Three bytes are available with following definitions and default contents (after reset).
Reg.-Name addr
D1
D2
D3
MRK-REG
(def. value)
1
0
GLOBAL
(def. value)
1
1
TEST
02H
TEST1
TEST2
ASYN
D4
D5
D6
D7
D8
00H
MRK1
MRK2
MRK3
1
MRK4
0
MRK5
0
MRK6
0
MRK7
1
MRK8
1
01H
MRK9
BD1
BD2
1
RxBw1
1
RxBw2
0
ZCEN
1
MMV
0
PWD
0
AgcH
digMix
noTSTin
TxSyn
FCdOn
(The default setting of the register "TEST" is always 00h.)
Bit-Name
MRK1-9
defines TX Mark Frequency (63.9k-140.55kHz)
BD1,2
defines Baud-Rate and Modulation-Depth
RXBW1,2
defines RX-BandPassFilter Bandwidth
ZCEN
disable ZeroCrossing TX-Sync
MMV
disables transmit Timeout
PWD
enables power down mode
TEST1,2
enables Test Mode 1-3
ASYN
disable synchronized receive data RXD
AgcH
hold AGC counter-state
digMix
enables digital mixer; analog mixer enabled by def.
noTSTin
TST-out function only for receiver debugging
TxSyn
enables TXD sampling with CLR/T rising-edge
Function
default val.
default function
453
131.85kHz
1, 1
2400Hz/1200Hz
1, 0
4.8kHz @132.45kHz
1
ZC-disabled
0
TimeOut enabled
0
powered up
0, 0
normal mode
0
sync. RXD
0
AGC-loop active
0
analog mixer
0
TSTin&out availab.
0
CLR/T gets synchronised
by TXD-edges
FCdOn
enables faster CD-ON timing (5/Bdrate)
0
Tcdon=(10/Bdrate)
AS5501 / AS5502 Multimode Powerline Modem
Data Sheet
Rev A, May 2000
Page 4/25
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