參數(shù)資料
型號(hào): AS5502
廠商: AUSTRIAMICROSYSTEMS AG
元件分類: 調(diào)制器/解調(diào)器
英文描述: Multimode Powerline-Modem
中文描述: 2.4 kbps DATA, MODEM, PDSO28
封裝: SOIC-28
文件頁數(shù): 11/26頁
文件大?。?/td> 315K
代理商: AS5502
To establish the frequency modulation, the output of the mark/space up/down-counter gets
added to Nmark. There has to be a smooth frequency-change from mark to space and from
space to mark within half the bit-time with 3 intermediate frequencies.
BD1
BD2
Fspace-Fmark
Baud-Rate (CKTX)
0
0
600Hz
600Hz
1
0
1200Hz
1200Hz
0
1
600Hz
1200Hz
1
1
1200Hz
2400Hz
M/S-UDC
0,1,2,3,4
0,2,4,6,8
0,1,2,3,4
0,2,4,6,8
BDclk (UDC-CLK)
4800Hz
9600Hz
9600Hz
19200Hz
Example with MRK-REG=8 => Fmark=81.75kHz; BD1,2=0 => dF=BRate=600Hz:
545
546 547 548
549
548 547
546
545
BDR*8
TXD (H=mark)
N
Fsynth / 16
(kHz)
81.75
81.90
82.05
82.20
82.35
82.20
82.05
81.75
81.90
(L=space)
In receive-mode(TxEn=1), a constant number Nmix defined by BD1 gets added to Nmark
instead of the output of the M/S-UDC. This gives a constant frequency which is used as
Mixer-frequency to fold the FSK-signal down to 2.7kHz or 5.4kHz. According to the
mixer-frequency the IF-SC-CLK is defined by the timing-block (see 1.1.3).
BD1
BD2
IFcenter
IFbandw
IF-SC-CLK
0
X
2700Hz
1200Hz
57.6kHz
1
X
5400Hz
2400Hz
115.2kHz
Nmix
20
40
BDclk (UDC-CLK)
4800Hz
9600Hz
The second frequency-synthesiser which is a similar structure as described for generating the
FSK-frequencies, is generating the target-frequency for the SCCLK-PLL. To get no
disturbing components, the phase-jitter of the synthesiser has to be reduced by the PLL.
There is a capacitor needed as external low-pass filter, to define the frequency response of the
PLL-loop. To generate the right target-frequency, one half of modulation-depth which is a
factor of 2 or 4 dependent on BD1 has to be added to Nmark. Since the center-frequency is a
very critical parameter, there is a possibility implemented for adjustment by wafersort-trim.
BD1 BD2 Fspace-Fmark
(Fcenter-Fmark)/150Hz
0
X
600Hz
2
1
X
1200Hz
4
(Itrim=0 ... 3 defined at wafer-sort)
Npll
MRK_REG + 426 + Itrim + 2
MRK_REG + 426 + Itrim + 4
AS5501 / AS5502 Multimode Powerline Modem
Data Sheet
Rev A, May 2000
Page 10/25
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