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參數(shù)資料
| 型號： | AS4SD1M16S-12 |
| 英文描述： | x16 SDRAM |
| 中文描述： | x16內(nèi)存 |
| 文件頁數(shù)： | 2/51頁 |
| 文件大?。?/td> | 1071K |
| 代理商： | AS4SD1M16S-12 |
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S DR A M
AS4SD16M16
Austin Semiconductor, Inc.
AS4SD16M16
Rev. 1.5 6/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
GENERAL DESCRIPTION
The 256MB SDRAM is a high-speed CMOS, dynamic ran-
dom-access memory containing 268,435,456 bits. It is internally
configured as a quad-bank DRAM with a synchronous inter-
face (all signals are registered on the positive edge of the clock
signal, CLK). Each of the 67,108,864-bit banks is organized as
8,192 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence. Ac-
cesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A12 select the row). The address bits
registered coincident with the READ or WRITE command are
used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4, or 8 locations, or the full page, with a
burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at
the end of the burst sequence.
The 256MB SDRAM uses an internal pipelined architec-
ture to achieve high-speed operation. This architecture is com-
patible with the 2
n
rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle
to achieve a high-speed, fully random operation. Precharging
one bank while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-speed, ran-
dom-access operation.
The 256Mb SDRAM is designed to operate in 3.3V memory
systems. An auto refresh mode is provided, along with a power-
saving, power-down mode. All inputs and outputs are LVTTL-
compatible.
SDRAMs offer substantial advances in DRAM operating
performance, including the ability to synchronously burst data
at a high data rate with automatic column-address generation,
the ability to interleave between internal banks to hide precharge
time and the capability to randomly change column addresses
on each clock cycle during a burst access.
FUNCTIONAL BLOCK DIAGRAM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS4SD1M16S-8A | x16 SDRAM |
| AS4SD4M16A2-10 | x16 SDRAM |
| AS4SD4M16A2-8 | x16 SDRAM |
| AS5010 | Voltage Reference |
| AS5010GN | Voltage Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4SD1M16S-8A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| AS4SD2M32 | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:512K x 32 x 4 Banks (64-Mb) Synchronous SDRAM |
| AS4SD2M32DGX-6ET | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:512K x 32 x 4 Banks (64-Mb) Synchronous SDRAM |
| AS4SD2M32DGX-6IT | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:512K x 32 x 4 Banks (64-Mb) Synchronous SDRAM |
| AS4SD2M32DGX-6XT | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:512K x 32 x 4 Banks (64-Mb) Synchronous SDRAM |
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