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參數(shù)資料
| 型號： | AS4C256K16E0-30JC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 5V 256Kx16 CMOS DRAM (EDO) |
| 中文描述： | 256K X 16 EDO DRAM, 30 ns, PDSO40 |
| 封裝： | 0.400 INCH, PLASTIC, SOJ-40 |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 644K |
| 代理商： | AS4C256K16E0-30JC |
AS4C256K16E0
4/11/01; v.1.1
Alliance Semiconductor
2 of 24
Functional description
The AS4C256K16E0 is a high performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16
bits. The AS4C256K16E0 is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high
speed, extremely low power and wide operating margins at component and system levels.
The AS4C256K16E0 features a high speed page mode operation in which high speed read, write and read-write are performed on any of the
512
×
16 bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease
the system level timing constraints associated with multiplexed addressing. Very fast CAS to output access time eases system design.
Refresh on the 512 address combinations of A0 to A8 during an 8 ms period is accomplished by performing any of the following:
RAS-only refresh cycles
Hidden refresh cycles
CAS-before-RAS refresh cycles
Normal read or write cycles
Self-refresh cycles*
The AS4C256K16E0 is available in standard 40-pin plastic SOJ and 40/44-pin TSOP II packages compatible with widely available automated
testing and insertion equipment. System level features include single power supply of 5V
±
0.5V tolerance and direct interface with TTL logic
families.
Logic block diagram
Recommended operating conditions
Parameter
(T
a
= 0°C to +70°C)
Max
*Self-refresh option is available for new generation device only. Contact Alliance for more information.
Symbol
Min
Typ
Unit
Supply voltage
V
CC
GND
4.5
5.0
5.5
V
0.0
0.0
0.0
V
Input voltage
V
IH
V
IL
2.4
–
V
CC
+ 1
0.8
V
–1.0
–
V
R
C
512×512×16
ARRAY
(4,194,304)
SENSE AMP
A0
A1
A2
A3
A4
A5
A6
A7
A8
V
CC
GND
A
R
COLUMN DECODER
RAS CLOCK
GENERATOR
SUBSTRATE
BIAS
GENERATOR
DATA
I/O
BUFFER
OE
RAS
UCAS
WE CLOCK
GENERATOR
WE
LCAS
I/O0 to I/O15
CAS CLOCK
GENERATOR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS4C256K16E0-35 | 5V 256Kx16 CMOS DRAM (EDO) |
| AS4C256K16E0-35JC | 5V 256Kx16 CMOS DRAM (EDO) |
| AS4C256K16E0-50 | 5V 256Kx16 CMOS DRAM (EDO) |
| AS4C256K16E0-50JC | 5V 256Kx16 CMOS DRAM (EDO) |
| AS4C256K16E0 | 5V 256K×16 CMOS DRAM (EDO)(5V 256K×16 CMOS動態(tài)RAM（擴展數(shù)據(jù)總線）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4C256K16E0-35 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 256Kx16 CMOS DRAM (EDO) |
| AS4C256K16E0-35JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 256Kx16 CMOS DRAM (EDO) |
| AS4C256K16E0-45JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 EDO Page Mode DRAM |
| AS4C256K16E0-50 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 256Kx16 CMOS DRAM (EDO) |
| AS4C256K16E050JC | 制造商:Alliance Memory Inc 功能描述: |
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