參數(shù)資料
型號: AS2702
廠商: AUSTRIAMICROSYSTEMS AG
英文描述: AS-Interface Slave IC
中文描述: AS - Interface的奴隸集成電路
文件頁數(shù): 8/18頁
文件大?。?/td> 119K
代理商: AS2702
AS-Interface Slave IC
AS2702 (SAP4.1)
Rev. C, January 2001
Page 8 of 18
input data to be valid within a specific time window relative to the HL-edge of the strobe,
after completion of the strobe’s L-phase.
If necessary, output data as per ha) and hb) can be easily latched with the LH-edge of strobe
DSTBn as they will remain valid for about 0.4 μs beyond as a minimum.
Care must be taken however, that signal delay added by external circuitry is lower for the
strobe than for the data.
Fig. 2: Timing of data transfer at data port D3, …, D0 relative to strobe DSTBn
The following table specifies the timing parameters relating to fig. 2:
6\PERO
tSTB
3DUDPHWHU
Delay DSTBn HL-edge to Dx
output data valid
DSTBn strobe width
Delay DSTBn LH-edge to Dx
output off
Input data valid time window
PLQ
PD[
1.5
8QLW
1RWH
μs
tDSTBn
tOUTOFF
6
6.8
1
μs
μs
1
2
0.2
tINP
10.5
12.5
μs
3
Notes:
1
2
3
Pulse width depends substantially on value of external pull-up resistor
Applies only to data port pins set to 'output / input' operation
Timing reference is DSTBn HL-edge.
Applies only to data port pins set to either 'output / input' or 'input' operation
Data in
Data out
Data in
Data out
t
DSTBn
+ t
OUTOFF
t
STB
t
DSTBn
+ 0.4 μs
t
DSTBn
t
INPmin
t
INPmax
Dx
Dx
DSTBn
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參數(shù)描述
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