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參數(shù)資料
| 型號： | AS1150-T |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | LVDS |
| 英文描述： | Quad, LVDS, RX, 500Mbps; Package Type: TSSOP-16 |
| 中文描述： | 四路LVDS接收器 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 417K |
| 代理商： | AS1150-T |
www.austriamicrosystems.com
Revision 1.19
11 - 15
AS1150/AS1151
Data Sheet - Applications
Cables and Connectors
Supported transmission media include printed circuit board traces, backplanes, and cables.
!
Use cables and connectors with matched differential impedance (typically 100
Ω
) to minimize impedance mis-
matches.
!
Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic
field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
!
Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable.
Termination
Due to the high data rates of LVDS drivers, matched termination will prevent the generation of any signal reflections,
and reduce EMI.
!
The AS1151 has integrated termination resistors connected across the inputs of each receiver. The value of the
integrated resistor is specified in
Table 3 on page 4
.
!
The AS1150 requires an external termination resistor. The termination resistor should match the differential imped-
ance of the transmission line and be placed as close to the receiver inputs as possible. Termination resistance val-
ues may range between 90 to 132
Ω
depending on the characteristic impedance of the transmission medium. Use
1% surface-mount resistors.
Board Layout
The device should be placed as close to the interface connector as possible to minimize LVDS trace length.
!
Keep the LVDS and any other digital signals separated from each other to reduce crosstalk.
!
Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals.
!
Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent
coupling.
!
Separate the input LVDS signals from the output signals planes with the power and ground planes for best results.
Figure 18. Propagation Delay and Transition Time Test Circuit
IN
x
+
50
Ω
50
Ω
IN
x
-
OUT
C
L
Pulse
Generator**
* 50
Ω
required for pulse generator.
** When testing the AS1151, adjust the pulse generator output
to account for internal termination resistor.
Receiver Enabled
1/4 AS1150, AS1151
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS1151 | 功能描述:IC LVDS QUAD RECEIVER 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AS1151-T | 功能描述:IC LVDS RECEIVER QUAD 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AS1152 | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| AS1152-T | 功能描述:IC LVDS RECEIVER QUAD 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AS1153 | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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