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參數(shù)資料
| 型號(hào)： | AR629AU9 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | MICROCIRCIT DATA SHEET |
| 中文描述： | MICROCIRCIT數(shù)據(jù)資料 |
| 文件頁數(shù)： | 11/17頁 |
| 文件大?。?/td> | 63K |
| 代理商： | AR629AU9 |
MNAR629A-X REV 0A0
MICROCIRCUIT DATA SHEET
Electrical Characteristics
AC: INTERNAL REGISTER/TRANSMIT DATA CHARACTERISTICS(Continued)
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC:
Vdd = Vcc = 5V +5%, Vss = GND, -55 C <TA<+125 C, CL = 50pF
SYMBOL
PARAMETER
CONDITIONS
NOTES
PIN-
NAME
MIN
MAX
UNIT
SUB-
GROUPS
TDERR
Delay from BUSQ
to Error Reg.
Valid (Non NXBA)
Vdd = 4.75V, Vdd = 5V +5%
15T
124T
nS
9, 10,
11
TDERR
BUSQ to error
register valid
(NXBA)
Vdd = 5V +5%
-340T
nS
9, 10,
11
TDFSTAC
Delay from XIVS
to STAC Low
Vdd = 4.75V, Vdd = 5.25V
5T-30
5T+35
nS
9, 10,
11
TDINT
Delay from IVR
valid to XIVS
14T
20T
nS
9, 10,
11
TDLWM
Delay from BUSQ
to LWM valid
Vdd = 5V +5%
20T
nS
9, 10,
11
TDLXIVS
Delay from 3rd
bit to leading
XIVS
Vdd = 4.75V, Vdd = 5.25V
3T-35
3T+55
nS
9, 10,
11
TDRSTAC
Delay from XIVS
to STAC High
Vdd = 4.75V, Vdd = 5.25V
2T-30
2T+35
nS
9, 10,
11
TDTXIVS
Delay from parity
bit to trailing
XIVS
Vdd = 4.75V, Vdd = 5V +5%
48T
96T
nS
9, 10,
11
THXAL
AO hold after
leading XIVS
falling edge
Vdd = 5V +5%
65T
nS
9, 10,
11
THXAT
AO hold after
trailing edge of
XIVS falling
Vdd = 4.75V, Vdd = 5.25V
4T-35
nS
9, 10,
11
TSAX
AO setup prior to
falling edge of
XIVS
Vdd = 4.75V, Vdd = 5.25V
2T-35
nS
9, 10,
11
TSDMA
Delay from bit 7
to DMA start
Vdd = 4.75V, Vdd = 5.25V
13T-35
13T+60
nS
9, 10,
11
TWBUSQ
Width of BUSQ
High during data
sync
Vdd = 5V +5%
30T
38T
nS
9, 10,
11
TWBUSQ1
BUS Quiet High
during
interstring gap
Vdd = 5V +5%
55T
64T
nS
9, 10,
11
TWXIVS
XIVS pulse Low
width
Vdd = 4.75V, Vdd = 5.25V
2T-10
2T+35
nS
9, 10,
11
11
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