ProASICPLUS Flash Family FPGAs v5.9 2-63 Asynchronous Write and Read to the Same" />
參數(shù)資料
型號: APA075-TQ144
廠商: Microsemi SoC
文件頁數(shù): 150/178頁
文件大?。?/td> 0K
描述: IC FPGA PROASIC+ 75K 144-TQFP
標準包裝: 60
系列: ProASICPLUS
RAM 位總計: 27648
輸入/輸出數(shù): 107
門數(shù): 75000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-TQFP(20x20)
ProASICPLUS Flash Family FPGAs
v5.9
2-63
Asynchronous Write and Read to the Same Location
Note: The plot shows the normal operation status.
Figure 2-36 Asynchronous Write and Read to the Same Location
Table 2-60 TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
ORDA
New DO access from RB
7.5
ns
ORDH
Old DO valid from RB
3.0
ns
OWRA
New DO access from WB
3.0
ns
OWRH
Old DO valid from WB
0.5
ns
RAWRS
RB
↓ or RADDR from WB ↓
5.0
ns
RAWRH
RB
↑ or RADDR from WB ↑
5.0
ns
Notes:
1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically
trigger a read operation which updates the read data. Refer to the ProASICPLUS RAM and FIFO Blocks application note for more
information.
2. Violation or RAWRS will disturb access to the OLD data.
3. Violation of RAWRH will disturb access to the NEWER data.
RB, RADDR
OLD
NEWER
NEW
t
ORDA
t
ORDH
t
OWRH
t
RAWRH
WB = {WRB+WBLKB}
DO
t
OWRA
t
RAWRS
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