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參數(shù)資料
| 型號： | AP160 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | ECONOLINE: REC3-S_DRW(Z)/H4,H6 - Safety standards and approval: EN 60950 certified, rated for 250VAV (LVD test report)- Applied for Ul 1950 Component Recognised Certification- 3W DIP Package- 4kVDC & 6kVDC Isolation- Regulated Output- Continuous Short Circiut Protection Auto-Restarting |
| 中文描述： | 8位單片機8KB的檢察官辦公室 |
| 文件頁數(shù)： | 7/25頁 |
| 文件大?。?/td> | 677K |
| 代理商： | AP160 |
AP160
TIMER2
Timer2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by
bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down
counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3.
Table 2.
T2CON – Timer/Counter 2 Control Register
T2CON Address = 0C8H
Bit
7
6
5
4
TF2
EXF2
RCLK
TCLK
Reset Value = 00000000
Bit Addressable
Symbol
TF2
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when
either RCLK = 1 or TCLK = 1.
EXF2
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt
routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode
(DCEN=1).
RCLK
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in
serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock.
TCLK
Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in
serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on
T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
triggered0.
CP/RL2
Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1.
CP/Rl2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX
when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on
Timer 2 overflow.
Table 3.
Timer 2 Operating Modes
RCLK+TCLK
CP/RL2
0
0
0
1
1
X
X
X
Timer2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine
cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.In the
Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2.
In this function, the external input is samples show a high in one cycle and a low in the next cycle, the count is incremented.
The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected.
Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is
1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be
held for at least one full machine cycle.
Version 0.0
7
AMIC Technology, Inc.
3
2
1
0
EXEN2
TR2
C/T2
CP/RL2
Function
TR2
1
1
1
0
MODE
16-Bit Auto-Reload
16-Bit Capture
Baud Rate Generator
(Off)
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