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參數(shù)資料
| 型號： | AOD420L |
| 廠商： | ALPHA |
| 英文描述： | N-Channel Enhancement Mode Field Effect Transistor |
| 中文描述： | N溝道增強型場效應(yīng)管 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 161K |
| 代理商： | AOD420L |
AOD420
Symbol
STATIC PARAMETERS
Drain-Source Breakdown Voltage
Min
Typ
Max
Units
BV
DSS
30
V
1
5
T
J
=55°C
I
GSS
V
GS(th)
I
D(ON)
100
3
nA
V
A
1
1.8
40
21
31
32.5
15.6
0.75
28
40
42
T
J
=125°C
m
g
FS
V
SD
I
S
DYNAMIC PARAMETERS
S
V
A
1
10
C
iss
C
oss
C
rss
R
g
SWITCHING PARAMETERS
710
120
72
1.1
850
pF
pF
pF
3.6
Q
g
(10V)
Q
g
(4.5V)
Q
gs
Q
gd
t
D(on)
t
r
t
D(off)
t
f
t
rr
Q
rr
14.4
7
2.6
2.7
5.6
2.4
15.6
2.2
13.4
4.4
18
8.4
nC
nC
nC
nC
ns
ns
ns
ns
21
ns
nC
THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING
OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,
FUNCTIONS AND RELIABILITY WITHOUT NOTICE.
Maximum Body-Diode Continuous Current
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On DelayTime
Turn-On Rise Time
Turn-Off DelayTime
Turn-Off Fall Time
V
GS
=10V, V
DS
=15V, I
D
=10A
Total Gate Charge
Total Gate Charge
Gate Source Charge
Gate Drain Charge
V
GS
=0V, V
DS
=15V, f=1MHz
V
GS
=10V, V
DS
=15V, R
L
=1.5
,
R
GEN
=3
Gate resistance
V
GS
=0V, V
DS
=0V, f=1MHz
m
V
GS
=4.5V, I
D
=7A
V
DS
=5V, I
D
=10A
I
S
=1A,V
GS
=0V
R
DS(ON)
Static Drain-Source On-Resistance
Forward Transconductance
Diode Forward Voltage
I
DSS
μ
A
Gate Threshold Voltage
On state drain current
V
DS
=V
GS
I
D
=250
μ
A
V
GS
=4.5V, V
DS
=5V
V
GS
=10V, I
D
=10A
V
DS
=24V, V
GS
=0V
V
DS
=0V, V
GS
= ±20V
Zero Gate Voltage Drain Current
Gate-Body leakage current
Electrical Characteristics (T
J
=25°C unless otherwise noted)
Parameter
Conditions
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
I
F
=10A, dI/dt=100A/
μ
s
I
D
=250
μ
A, V
GS
=0V
I
F
=10A, dI/dt=100A/
μ
s
A: The value of R
θ
JA
is measured with the device mounted on 1in
2
FR-4 board with 2oz. Copper, in a still air environment with T
A
=25°C. The Power
dissipation P
DSM
is based on R
θ
JA
and the maximum allowed junction temperature of 150°C. The value in any given application depends on the user's
specific board design, and the maximum temperature of 175°C may be used if the PCB allows it.
B. The power dissipation P
D
is based on T
J(MAX)
=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation
limit for cases where additional heatsinking is used.
C: Repetitive rating, pulse width limited by junction temperature T
J(MAX)
=175°C.
D. The R
θ
JA
is the sum of the thermal impedence from junction to case R
θ
JC
and case to ambient.
E. The static characteristics in Figures 1 to 6 are obtained using <300
μ
s pulses, duty cycle 0.5% max.
F. These tests are performed with the device mounted on 1 in
2
FR-4 board with 2oz. Copper, in a still air environment with T
A
=25°C. The SOA curve
provides a single pulse rating.
G. The maximum current rating is limited by bond-wires. Rev4: August 2005
Alpha & Omega Semiconductor, Ltd.
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