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參數(shù)資料
| 型號： | AND8001D |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | ODD NUMBER DIVIDE BY COUNTERS WITH 50% OUTPUTS AND SYNCHRONOUS CLOCKS |
| 中文描述： | 奇數(shù)除以計數(shù)器與50％的產(chǎn)出和同步時鐘 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 67K |
| 代理商： | AND8001D |
AND8001/D
http://onsemi.com
7
Maps show:
Ja = 1
Ka = 1
JB = AC*
Kb = A
Jc = AB
Kc = A
Figure 8 shows the implementation.
Figure 8. Synchronous Divide By 12
CLK
AQ
BQ
CQ
OUT, DQ
Q
Q
J
C
Q
Q
J
C
Clk
Q
Q
J
C
K
50% Out
Ja = 1
Ka = 1
Jb = AC
Kb = A
Jc = AB
Kc = A
Jd = ACD
Kd = ACD
K
K
Q
Q
J
C
K
H
A
B
C
D
A
0
1
0
1
0
1
0
1
0
1
0
1
B
0
0
1
1
0
0
0
0
1
1
0
0
C
0
0
0
0
1
1
0
0
0
0
1
1
D
0
0
0
0
0
0*
1
1
1
1
1
1*
0
1
2
3
4
5
6
7
8
9
10
11
The truth table shows that the FF ”D”
must change state at 5 and 13
Examination of the truth table shows that the FF ”D” must
decode a 5 and a 13 in order to make the desire 50% function.
The inputs to the ”D” FF are J = ACD* and K = ACD and
requires 3 input AND gates. For larger counters the inputs
on the AND gates will need to increase to reach the desired
configuration; However for the single digit integers such as
3, 5, 7, & 9 to realize 6, 10, 14, & 18 a fan in of three is max.
The methods are expandable. A little observation,
thinking, and logic typing will allow the designer to
minimize the component count and skew on this type of
counter.
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