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參數(shù)資料
| 型號(hào)： | AND8001D |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | ODD NUMBER DIVIDE BY COUNTERS WITH 50% OUTPUTS AND SYNCHRONOUS CLOCKS |
| 中文描述： | 奇數(shù)除以計(jì)數(shù)器與50％的產(chǎn)出和同步時(shí)鐘 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 67K |
| 代理商： | AND8001D |
AND8001/D
http://onsemi.com
4
Figure 4.
Q
Q
D
C
Divide By 9 50% Counter
Q
Q
D
C
50%
Out
Clk
A
E
Q
Q
D
C
B
Q
Q
D
C
C
Q
Q
D
C
D
C
C
Clk
AQ
BQ
CQ
OUT
DQ
EQ
Choosing to use ”C” as the flip flop to delay by a 1/2 clock
cycle is necessary to accomplish the 50% output required
when ”ANDed” with ”E”.
Another Synchronous 50% counter for Divide By 6, 10,
12, 14, 18, etc. can be realized by the additions of a J K FF
and some gates. Other types of FF’s may be used.
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