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參數(shù)資料
| 型號： | AND8001D |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | ODD NUMBER DIVIDE BY COUNTERS WITH 50% OUTPUTS AND SYNCHRONOUS CLOCKS |
| 中文描述： | 奇數(shù)除以計數(shù)器與50％的產(chǎn)出和同步時鐘 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 67K |
| 代理商： | AND8001D |
AND8001/D
http://onsemi.com
5
Take the before mentioned Divide By 3 add a J K and a
divide by 6, 50% duty cycle, synchronous counter is realized
as shown in Figure 5.
Figure 5.
Q
Q
D
C
Q
Q
D
C
Clk
Q
Q
J
C
K
50% Out
Divide By 6 50% Out
Clk
AQ
BQ
OUT, CQ
A
B
C
Of course, there are better ways to realize a Divide By 6
but it does demonstrate how the method works. Note this
configuration does not require a 50% input clock duty cycle
and it is synchronous. This type of configuration could be
useful in a clock generating PLL chip where a Divide By 3
and Divide By 6 are needed to synchronize two signals as
shown in figure 6.
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