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參數(shù)資料
| 型號(hào)： | AN6591FJM |
| 廠商： | PANASONIC CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Transmission / reception, single chip PLL IC for PHS, cordless telephone |
| 中文描述： | TELECOM, CORDLESS, RF AND BASEBAND CIRCUIT, PQCC44 |
| 封裝： | 6 X 6 MM, PLASTIC, QFN-44 |
| 文件頁數(shù)： | 14/21頁 |
| 文件大?。?/td> | 391K |
| 代理商： | AN6591FJM |
AN6591FJM
14
SDM00007BEB
■
Technical Data
1. Serial data interface specifications
Carrier data is transferred in 23-bit serial data transfer. The serial data is set at the clock falling edge and latched
onto the synthesizer at the clock rising edge. It is necessary to input a single STROBE pulse when the 23-bit serial
data transfer is completed.
1) Serial interface of 1st synthesizer
1st synthesizer serial data input format
N10
MSB
LSB
X: don't care
N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 A6 A5 A4 A3 A2 A1 A0 PD
P
TC C1 C0
X
X
X
TO
X R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
T1
T0
C1 C0
←
N data input direction
f
out
=
(P
×
N
+
A)
×
f
in
/ R
Possible set range: 1st
A
=
0 to 127 or 63, N
=
5 to 2
047 (N
>
A)
R
=
5 to 16
383
C0
C1
1
0
1
1
1st synthesizer R counter frequency
dividing ratio setting
1st synthesizer A / N counter frequency
dividing ratio setting
PD
Phase comparator
polarity selection
P
Prescaler frequency
dividing ratio
TC
Counter test
mode setting
TO
Output pin test
0
negative
1
positive
128 / 129
64 / 65
LD output
Counter output
normal
test
T0
T1
0
0
0
1
2nd synthesizer R counter output
2nd synthesizer N counter output
1
0
1
1
1st synthesizer R counter output
1st synthesizer N counter output
Data
Clock
STROBE
22
21
20
19
18
2
(t
1
, t
2
≥
50 ns)
1
0
t
1
t
2
2) Serial transfer timing
Timing chart
(1) Control bit
(2) Test contents
(3) Data contents
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