參數(shù)資料
型號(hào)： AN6591FJM
廠商： PANASONIC CORP
元件分類： 無(wú)繩電話/電話
英文描述： Transmission / reception, single chip PLL IC for PHS, cordless telephone
中文描述： TELECOM, CORDLESS, RF AND BASEBAND CIRCUIT, PQCC44
封裝： 6 X 6 MM, PLASTIC, QFN-44
文件頁(yè)數(shù)： 5/21頁(yè)
文件大小： 391K
代理商： AN6591FJM
AN6591FJM
5
SDM00007BEB
Parameter
Symbol Test
Conditions
Min
Typ
Max
Unit
circuit
1st local leakage suppression
CL1
1
Lo1
=
233.15 MHz,
10 dBm
Lo2
=
1
672.5 MHz,
10 dBm
V
APC
=
2.75 V
25
20
dBc
2nd local leakage suppression CL2
1
Lo1
=
233.15 MHz,
10 dBm
Lo2
=
1
672.5 MHz,
10 dBm
V
APC
=
2.75 V
15
10
dBc
In-band output level deviation
P
1
Lo1
=
233.15 MHz,
10 dBm
Lo2
=
1
660 MHz to 1
687 MHz,
10 dBm, V
APC
=
2.2 V
1.0
dB
Adjacent channel leakage
power suppression
(600 kHz detuning)
BL1
1
Lo1
=
233.15 MHz,
10 dBm
Lo2
=
1
672.5 MHz,
10 dBm
V
APC
=
2.75 V
60
dBc
Modulation accuracy
EVM
1
Lo1
=
233.15 MHz,
10 dBm
Lo2
=
1
672.5 MHz,
10 dBm
V
APC
=
2.2 V
3
5
%[rms]
Min. output level
Pmin
1
Lo1
=
233.15 MHz,
10 dBm
Lo2
=
1
672.5 MHz,
10 dBm
V
APC
=
1.0 V
30
25
dBm
RF
+
233.15 MHz
leakage suppression
IIL
1
Lo1
=
233.15 MHz,
10 dBm
Lo2
=
1
672.5 MHz,
10 dBm
V
APC
=
2.75 V
36
dBc
Mixer output resistance
Rmix
2
No signal input
330
■
Electrical Characteristics at T
a
=
25
°
C (continued)
Parameter
Symbol Test
Conditions
Min
Typ
Max
Unit
circuit
Current consumption 1 (PLL)
I
CC1
1
1st PLL and 2nd PLL blocks are
simultaneously turned on.
3.7
5.4
7.0
mA
Current consumption 2 (PLL)
I
CC2
1
1st PLL block is turned on while the
2nd PLL block is turned off.
3.0
4.4
5.7
mA
Current consumption 3 (PLL)
I
CC3
1
1st PLL block is turned off while the
2nd PLL block is turned on.
1.2
1.7
2.2
mA
Current consumption 4 (PLL)
I
CC4
1
Power save mode
15
10
0
10
μ
A
1st RF input level
V
RFIN
1
f
RFIN
=
1
500 MHz to 1
800 MHz
f
IFIN
=
120 MHz to 300 MHz
f
REFIN
=
10 MHz to 25 MHz
2
+
6
dBm
2nd IF input level
V
IFIN
1
dBm
Reference signal input level V
REFIN
1
0.2
1.2
Note) Unless otherwise specified, V
CC
is 3.0 V and reference signal input level V
REFIN
is 0.6 V[p-p] at f
REFIN
=
19.2 MHz.
Note) Unless otherwise specified, V
CC
= V
CC1
= V
CC2
= 3.0 V
I / Q signal: 0.5 V[p-p] in both phases, DC bias: 1.5 V
CL1, CL2,
P
,
BL1, EVM, Pmin, IIL : PN9-level modulated wave.
Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
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