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參數(shù)資料
| 型號： | AN246 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Transmission lines and terminations with Philips Advanced Logic families |
| 中文描述： | 傳輸線，并與飛利浦先進邏輯家庭終端 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 216K |
| 代理商： | AN246 |
Philips Semiconductors
Application Note
AN246
Transmission lines and terminations
with Philips Logic families
1998 Feb 05
12
No DC current flows during quiescent high or low logic levels, but an
AC current path is available through C1 to terminate the line.
Choose XC to be a small percentage of Z
O
at the operating
frequency of:
Eq. 15
f
1
2T
r
where T
r
is the faster of the rise or fall time
Also, for DC balanced signals with 50% duty cycle, choose C such
that Z
O
C is much greater than the pulse period. For DC imbalanced
signals, choose C such that Z
O
C is much greater than the rise time
but much smaller than half the pulse period.
Provided that the duty cycle is 50%, the average voltage across C1
is midway between the driver high and low output levels. R1 will
also have half the voltage swing always across it. The power
dissipation across R1 will be:
Eq. 16
P
V
OH
–
VOL
2
2
Z
O
(V
OH
– V
OL
)
2
4Z
O
Another method of end termination is shown in Figure 20.
Z
O
Z
O
Z
O
R
1
|| R
2
= Z
O
’
V
CC
R
1
R
2
V
CC
R
1
R
2
SH00124
Figure 20. Party bus dual termination
The same principles should be applied to this method as in the
Thevenin termination. Note that drivers will need to be strong, such
as the BiCMOS devices, since they will have to drive half the value
of Z
O
.
The last method of end termination discussed in this paper is diode
clamp termination shown in Figure 21:
Z
O
Driver
SH00123
V
CC
Figure 21. Diode clamp termination
The advantages are that it dissipates no power and it adds no delay
to the net. The method is good to clamp overshoot and undershoot
provided that it is fast enough to react to the rising or falling edge.
The disadvantage is that it won’t limit overshoot on 5 volt TTL
drivers such as ABT. Also, it can’t guarantee monotonicity on weak
drivers.
CONCLUSION
Philips Semiconductors offers various advanced CMOS and
BiCMOS families for high speed bus applications. This paper
discussed aspects of transmission line effects with these families.
Critical line length, line impedance, loading, and drive capability of
different product families was examined. Impedance mismatches
and reflections were discussed along with various termination
solutions. Considerations of these various factors will help solve
signal integrity issues in a design, and these factors need to be
considered with their tradeoffs to satisfy the system design needs.
To help make design efforts easier, Philips Semiconductors offers
free SPICE models for our 3V and 5V product families to aid in
signal integrity evaluation. The models help reduce design time by
eliminating time consuming efforts of reflection and Bergeron
diagrams, and they also help predict signal integrity prior to board
layout.
ACKNOWLEDGEMENTS
Thanks to Tinus van de Wouw and Jeff West for their help and data.
REFERENCES
1. Drs. Howard Johnson and Martin Graham, High-Speed Digital
Design Englewood Cliffs: PTR Prentice Hall, 1993.
2. James Buchanan, Signal and Power Integrity in Digital Systems:
TTL, CMOS, and BiCMOS New York: McGraw-Hill, 1996.
3. Steve Kaufer, Termination Improves Board Signal Quality
Electronic Engineering Times: September 2, 1996, p. 44, p. 74.
4. High Performance ECL Data Book: Design Guide Section
System Interconnect. Motorola, Inc.: 1993.
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