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參數(shù)資料
| 型號： | AN246 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Transmission lines and terminations with Philips Advanced Logic families |
| 中文描述： | 傳輸線，并與飛利浦先進(jìn)邏輯家庭終端 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 216K |
| 代理商： | AN246 |
Philips Semiconductors
Application Note
AN246
Transmission lines and terminations
with Philips Logic families
1998 Feb 05
11
Figure 16 shows another method of series termination.
R
S
R
S
R
S
Z
O
Z
O
Z
O
R
S
SH00120
Figure 16. Series stub termination
Note that the drivers at the end will be driving RS + Z
O
. Drivers in
the middle should be strong enough to drive RS + Z
O
/2. Again,
keep stub lengths short.
End Terminations
End terminated line are recommended for distributed loads, and
several methods can be used such as parallel, AC, and diode clamp
methods. Figure 17 shows two parallel termination schemes.
Z
O
SH00121
Z
O
V
CC
R
T
= Z
O
R
T
= Z
O
Figure 17. Parallel terminations
With this method, the termination resistance is matched to the
effective line impedance. The advantage is that this method allows
for incident wave switching. The disadvantages are that you need
an extremely strong driver and it consumes high static power.
To reduce the drive requirements and power dissipation for this
configuration, a more practical parallel Thevenin termination is
shown in Figure 18 can be used.
Z
O
Z
O
V
CC
Receiver A
Receiver B
Receiver C
R
1
R
2
Driver
R
1
|| R
2
= Z
O
’
SH00122
Figure 18. Daisy chain topology with split resistor Thevenin
termination
This method is suitable for ABT, LVT, and ALVT families but not
recommended for low voltage CMOS logic if power dissipation is a
concern. The termination is placed at the end of the line as close to
the receiver as possible.
If this termination technique is used on LVC and ALVC drivers, take
precaution not to connect the pull-up resistor to a 5 volt supply in a
mixed 3 volt/5 volt system. This can cause 5 volt supply current to
flow to the 3 volt supply through the upper PMOS transistor’s
parasitic diode of the driver output during the active high state.
If used on a 3-State bus, avoid biasing the receiver input at its
threshold switching voltage which is about 1.5 V for BiCMOS and
CMOS TTL level inputs. Inputs left floating around the threshold
region can consume excessive current or cause oscillations. You
can use the following formula to determine values for R1 and R2 if
they are not equal:
Eq. 13
R
1
Z
O
V
CC
V
T
and R
2
Z
O
V
CC
V
CC
V
T
where V
T
= termination voltage.
A good termination voltage to choose is 2.5 V for TTL thresholds.
Assuming a 50% duty cycle, the average power dissipation of the
resistors will be:
Eq. 14
P
0.5
V
OH
2
V
OL
2
2R
2
(V
CC
– V
OH
)
2
(V
CC
– V
OL
)
2
2R
1
Another method to reduce quiescent power dissipation is AC
termination shown in Figure 19. This method is recommended for
distributed loads or when static power consumption is a concern.
Z
O
R
1
Driver
R
1
= Z
O
C
1
SH00125
Figure 19. AC termination
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