
The Essentials of Enhanced Time Processing Unit, Rev. 1
The Microengine
Freescale Semiconductor
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128 local parameters (512 bytes) and 256 shared global parameters (2 Kbytes). The channels can also use
indexed addressing to access data anywhere in data RAM of up to 16k.
The local parameter space for each
channel is determined by the host at system initialization, providing the most efficient distribution of the
available parameters. A function such as pulse width modulation may be allocated two control parameters,
while another such as a stepper motor drive may require dozens. Provision has been made to enable DMA
access of the data RAM to greatly increase the virtual size of the data memory.
The parameters are 32 bits wide to match the bus width of the core processor. Since the eTPU is a 24-bit
machine, various means are provided for efficient transfer of parameter information, including sign
extension and separate accessing of the most significant byte. Transfers between the eTPU and the host
can be protected for coherency by using hardware supported semaphores.
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The Microengine
The TPU was designed to service the channel timer hardware as efficiently as possible, by providing a
small, microcoded instruction map that could perform several operations in parallel. There were five
microcode formats with as many as 12 operations that could be executed in parallel. All microinstructions
executed in a single microcycle (2 clock cycles), except where there was a collision on memory access
between the CPU and eTPU.
Figure 1. TPU Instruction Set Coding
Because of more complex options in the greatly expanded channel hardware, the eTPU instruction map is
not nearly as simple and small, but many instruction combinations can still be done in a single cycle.
Familiar routines where a microengine stores information latched by the channel hardware, and the