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| 型號： | AN1504D |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | Metastability and the ECLinPS Family |
| 中文描述： | 亞穩(wěn)態(tài)和業(yè)界的EClinPS家庭 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 135K |
| 代理商： | AN1504D |
AN1504/D
http://onsemi.com
7
The values for f
C
and f
D
were specified as 100 MHz and
75 MHz, respectively. Assuming the D flip
flop is an
ON Semiconductor 10E151, a worse case value of
propagation delay (Tp) of 800 psec is obtained from the
ECLinPS Device Data Book. The value of t is given in
Table 2 as 185 psec. Substituting these values into
Equation 3 yields:
MTBF
At this point the system designer must specify an
acceptable MTBF. For this example an MTBF of 5 years is
assumed. Therefore the value of t is calculated to be
t = 2.83 nsec
From the relationship
t = T
D
T
P
the value of T
D
is calculated to be
T
D
= 3.63 nsec
Thus for an MTBF of 5 years the designer should delay the
clocking of the data from the output of the flip
flop into
System 2 by 3.63 nsec.
1 (2 * fC* fD* TP* 10
( t 185 psec))
(eq. 6)
Conclusion
Metastability has become a critical issue with system
designers. In order to better serve our customers,
ON Semiconductor has characterized the ECLinPS family
for metastability using the concept of a failure window. The
nominal flip
flop resolution time constant for the ECLinPS
family, excluding the E131 and E431 devices as these
flip
flops use alternative architectures, has been determined
to be 185 psec. The resolution time constant for the E131 and
E431 devices is 200 psec and 125 psec, respectively. Thus
the system designer can use the value of in conjunction
with Equation 3 to determine the metastable induced excess
delay for a specified MTBF. Although this application note
does not present a method for avoiding metastability, it does
provide a means for the designer to quantitatively
incorporate metastability in their designs.
References
1. Stoll, P. “How to Avoid Synchronization Problems” VLSI
Design, November/December 1982. pp. 56
59.
2. Nootbaar, K. “Design, Testing, and Application of a
Metastable
Hardened flip
flop,” Wescon/87, Section
16
2 pp. 1
9.
SYSTEM 2 INPUT
SYSTEM 2
Q
CLOCK
DATA
D FLIP
FLOP
SYSTEM 2
CLOCK
SYSTEM 1
OUTPUT
SYSTEM 1
CLOCK
SYSTEM 1
Figure 12. System Example
100 MHz
75 MHz
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