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參數(shù)資料
| 型號(hào)： | AN1406 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | DESIGNING WITH PECL (ECL AT + 5.0) |
| 中文描述： | 具有PECL設(shè)計(jì)（ECL在5.0） |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 117K |
| 代理商： | AN1406 |
AN1406/D
http://onsemi.com
4
The traditional choice of a negative power supply for ECL
is the result of the upper supply rail being used as the
reference for the I/0 and internal switching bias levels of the
technology. Since these critical parameters are referenced to
the upper rail any noise on this rail will couple 1:1 onto them;
the result will be reduced noise margins in the design.
Because, in general, it is a simpler task to keep a ground rail
relatively noise free, it is beneficial to use the ground rail as
this reference. However when careful attention is paid to the
power supply design, PECL can be used to optimize system
performance. Once again the use of differential PECL will
simplify the designer’s task as the noise margins of the
system will be doubled and any noise riding on the upper
VCC rail will appear as common mode noise; common mode
noise will be rejected by the differential receiver.
MECL to PECL DC Level Conversion
Although using ECL on positive power supplies is
feasible, as with any high speed design there are areas in
which special attention should be placed. When using ECL
devices with positive supplies the input output voltage levels
need to be translated. This translation is a relatively simple
task. Since these levels are referenced off of the most
positive rail, VCC, the following equation can be used to
calculate the various specified DC levels for a PECL device:
PECL Level = VCCNEW – |Specification Level|
As an example, the VOHMAX level for a 10H device
operating with a VCC of 5.0V at 25
°
C would be as follows:
PECL Level = 5.0V – |–0.81V|
PECL Level = (5.0 – 0.81)V = 4.19V
The same procedure can be followed to calculate all of the
DC levels, including VBB for any ECL device. Table 2, on
page 4, outlines the various PECL levels for a VCC of 5.0V
for both the 10H and 100K ECL standards. As mentioned
earlier any changes in VCC will show up 1:1 on the output
DC levels. Therefore any tolerance values for VCC can be
transferred to the device I/0 levels by simply adding or
subtracting the VCC tolerance values from those values
provided in Table 2.
PECL Termination Schemes
PECL outputs can be terminated in all of the same ways
standard ECL, this would be expected since an ECL and a
PECL device are one in the same. Figure 3 illustrates the
various output termination schemes utilized in typical ECL
systems. For best performance the open line technique in
Figure 3 would not be used except for very short
interconnect between devices; the definition of short can be
found in the various design guides for the different ECL
families. In general for the fastest performance and the
ability to drive distributive loads the parallel termination
techniques are the best choice. However occasions may arise
where a long uncontrolled or variable impedance line may
need to be driven; in this case the series termination
technique would be appropriate. For a more thorough
discourse on when and where to use the various termination
techniques the reader is referred to the MECL System
Design Handbook (HB205/D) and the design guide in the
ECLinPS Databook (DL140/D). The parallel termination
scheme of Figure 3 requires an extra VTT power supply for
the impedance matching load resistor. In a system which is
built mainly in CMOS/TTL this extra power supply
requirement may prohibit the use of this technique. The
other schemes of Figure 3 use only the existing positive
supply and ground and thus may be more attractive for the
CMOS/ TTL based machine.
Table 2. ECL/PECL DC Level Conversion for VCC = 5.0V
10E Characteristics
100E Characteristics
0
°
C
25
°
C
85
°
C
0 to 85
°
C
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
VOH
–1.02/3.98
–0.84/4.16
–0.98/4.02
–0.81/4.19
–0.92/4.08
–0.735/4.265
–1.025/3.975
–0.880/4.120
V
VOL
–1.95/3.05
–1.63/3.37
–1.95/3.05
–1.63/3.37
–1.95/3.05
–1.600/3.400
–1.810/3.190
–1.620/3.380
V
VOHA
—
—
—
—
—
—
—
–1.610/3.390
V
VOLA
—
—
—
—
—
—
–1.035/3.965
—
V
VIH
–1.17/3.83
–0.84/4.16
–1.13/3.87
–0.81/4.19
–1.07/3.93
–0.735/4.265
–1.165/3.835
–0.880/4.120
V
VIL
–1.95/3.05
–1.48/3.52
–1.95/3.05
–1.48/3.52
–1.95/3.05
–1.450/3.550
–1.810/3.190
–1.475/3.525
V
VBB
–1.38/3.62
–1.27/3.73
–1.35/3.65
–1.25/3.75
–1.31/3.69
–1.190/3.810
–1.380/3.620
–1.260/3.740
V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AN1406/D | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:DESIGNING WITH PECL (ECL AT + 5.0) |
| AN1406D | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V / 5V ECL 2-Input Differential XOR/XNOR |
| AN14-17A | 制造商:AN# - MILITARY 功能描述: |
| AN1431 | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:Surface-mount Adjustable Output Shunt Regulator |
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