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參數(shù)資料
| 型號： | AN1406 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | DESIGNING WITH PECL (ECL AT + 5.0) |
| 中文描述： | 具有PECL設(shè)計（ECL在5.0） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 117K |
| 代理商： | AN1406 |
Semiconductor Components Industries, LLC, 1999
September, 1999 – Rev. 2
1
Publication Order Number:
AN1406/D
The High Speed Solution for the
CMOS/TTL Designer
Prepared by
Cleon Petty
Todd Pearson
ECL Applications Engineering
This application note provides detailed information on designing with Positive Emitter Coupled Logic (PECL) devices.
Introduction
PECL, or Positive Emitter Coupled Logic, is nothing
more than standard ECL devices run off of a positive power
supply. Because ECL, and therefore PECL, has long been
the “black magic” of the logic world many misconceptions
and falsehoods have arisen concerning its use. However,
many system problems which are difficult to address with
TTL or CMOS technologies are ideally suited to the
strengths of ECL. By breaking through the wall of
misinformation concerning the use of ECL, the TTL and
CMOS designers can arm themselves with a powerful
weapon to attack the most difficult of high speed problems.
It has long been accepted that ECL devices provide the
ultimate in logic speed; it is equally well known that the
price for this speed is a greater need for attention to detail in
the design and layout of the system PC boards. Because this
requirement stems only from the speed performance aspect
of ECL devices, as the speed performance of any logic
technology increases these same requirements will hold. As
can be seen in Table 1 the current state–of–the–art TTL and
CMOS logic families have attained performance levels
which require controlled impedance interconnect for even
relatively short distances between source and load. As a
result system designers who are using state–of–the–art TTL
or CMOS logic are already forced to deal with the special
requirements of high speed logic; thus it is a relatively small
step to extend their thinking from a TTL and CMOS bias to
include ECL devices where their special characteristics will
simplify the design task.
Table 1. Relative Logic Speeds
Logic
Family
Typical Output
Rise/Fall
Maximum Open Line
Length (Lmax)*
3
″
10KH
1.0ns
ECLinPS
400ps
1
″
FAST
2.0ns
6
″
FACT
1.5ns
4
″
* Approximate for stripline interconnect (Lmax = Tr/2Tpd)
System Advantages of ECL
The most obvious area to incorporate ECL into an
otherwise CMOS/TTL design would be for a subsystem
which requires very fast data or signal processing. Although
this is the most obvious it may also be the least common.
Because of the need for translation between ECL and
CMOS/TTL technologies the performance gain must be
greater than the overhead required to translate back and forth
between technologies. With typical delays of six to seven
nanoseconds for translating between technologies, a
significant portion of the logic would need to be realized
using ECL for the overall system performance to improve.
However, for very high speed subsystem requirements ECL
may very well provide the best system solution.
Transmission Line Driving
Many of the inherent features of an ECL device make it
ideal for driving long, controlled impedance lines. The low
impedance of the open emitter outputs and high input
impedance of any standard ECL device make it ideally
suited for driving controlled impedance lines. Although
designed to drive 50
lines an ECL device is equally adept
at driving lines of impedances of up to 130
without
significant changes in the AC characteristics of the device.
Although some of the newer CMOS/TTL families have the
ability to drive 50
lines many require special driver circuits
to supply the necessary currents to drive low impedance
transmission interconnect. In addition the large output
swings and relatively fast output slew rates of today’s high
performance CMOS/TTL devices exacerbate the problems
of crosstalk and EMI radiation. The problems of crosstalk
and EMI radiation, along with common mode noise and
signal amplitude losses, can be alleviated to a great degree
with the use of differential interconnect. Because of their
architectures, neither CMOS nor TTL devices are capable of
differential communication. The differential amplifier input
structure and complimentary outputs of ECL devices make
them perfectly suited for differential applications. As a
result, for systems requiring signal transmission between
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APPLICATION NOTE
相關(guān)PDF資料 |
PDF描述 |
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| AN1504 | Metastability and the ECLinPS Family |
| AN1504D | Metastability and the ECLinPS Family |
| AN1568 | Interfacing Between LVDS and ECL |
| AN1568D | Interfacing Between LVDS and ECL |
| AN1593 | LOW COST 1.0 A CURRENT SOURCE FOR BATTERY CHARGERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AN1406/D | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:DESIGNING WITH PECL (ECL AT + 5.0) |
| AN1406D | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V / 5V ECL 2-Input Differential XOR/XNOR |
| AN14-17A | 制造商:AN# - MILITARY 功能描述: |
| AN1431 | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:Surface-mount Adjustable Output Shunt Regulator |
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