參數(shù)資料
型號： AN103
廠商： Electronic Theatre Controls, Inc.
英文描述： The FET Constant-Current Source/Limiter
中文描述： 場效應管的恒流源/限制器
文件頁數(shù)： 1/5頁
文件大?。?/td> 56K
代理商： AN103
AN103
Siliconix
10-Mar-97
1
The FET Constant-Current Source/Limiter
Introduction
The combination of low associated operating voltage and
high output impedance makes the FET attractive as a
constant-current source. An adjustable-current source (Fig-
ure 1) may be built with a FET, a variable resistor, and a
small battery. For optimum thermal stability, the FET should
be biased near the zero temperature coefficient point.
D
S
–
+
Figure 1.
Field-Effect Transistor Current Source
R
S
R
L
NO TAG
Whenever the FET is operated in the current saturated re-
gion, its output conductance is very low. This occurs
whenever the drain-source voltage V
DS
is at least 50%
greater than the cut-off voltage V
GS(off)
. The FET may be
biased to operate as a constant-current source at any cur-
rent below its saturation current I
DSS
.
Basic Source Biasing
For a given device where I
DSS
and V
GS(off)
are known, the
approximate V
GS
required for a given I
D
is
(1)
V
GS
V
GS(off)
1 –
I
D
I
DSS
1 k
where k can vary from 1.8 to 2.0, depending on device ge-
ometry. If K = 2.0, the series resistor R
S
required between
source and gate is
(2)
R
S
V
GS
I
D
or
R
S
V
GS(off)
I
D
1–
I
D
I
DSS
A change in supply voltage or a change in load imped-
ance, will change I
D
by only a small factor because of the
low output conductance g
oss
.
I
D
= ( V
DS
)(g
oss
)
(3)
The value of g
oss
is an important consideration in the ac-
curacy of a constant-current source where the supply volt-
age may vary. As g
oss
may range from less than 1 S to
more than 50 S according to the FET type, the dynamic
impedance can be greater than 1 M to less than 20 k .
This corresponds to a current stability range of 1 A to
50 A per volt. The value of g
oss
also depends on the op-
erating point. Output conductance g
oss
decrease approxi-
mately linearly with I
D
. The relationship is
(4)
I
D
I
DSS
g
oss
g
oss
where g
oss
= g
oss
(5)
when V
GS
= 0
(6)
So as V
GS
→
V
GS(off)
, g
oss
→
Zero. For best regulation,
I
D
must be considerably less than I
DSS
.
Cascading for Low g
oss
It is possible to achieve much lower g
oss
per unit I
D
by
cascading two FETs, as shown in Figure 2.
D
S
–
+
S
D
Figure 2.
Cascade FET Current Source
V
DD
R
S
R
L
Q
2
Q
1
Updates to this app note may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70596.
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