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| 型號(hào)： | AN-90 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 74C Family Characteristics |
| 中文描述： | 74C條家庭特征 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 209K |
| 代理商： | AN-90 |
voltages. To obtain actual power consumption find the nor-
malized power for a particular V
CC
and frequency, then mul-
tiply by C
PD
+ C
L
.
As an example let’s find the total power consumption for an
MM74C00 operating at f = 100 kHz, V
= 10V and C
= 50
pF. From the curve, normalized power per gate equals 10
μW/pF. From the data sheet C
PD
= 12 pF; therefore, actual
power per gate is:
Up to this point the discussion of power consumption has
been limited to simple gate functions. Power consumption
for an MSI function is more complex but the same technique
just derived applies. To demonstrate the technique let’s com-
pute the total power consumption of a MM74C161, four bit
binary counter, at V
CC
= 10V, f = 1 MHz and C
L
= 50 pF on
each output.
The no load power is still given by P (no load) = C
V
2 f.
This demonstrates the usefulness of the concept of the inter-
nal capacitance, C
PD
. Even though the circuit is very com-
plex and has many nodes charging and discharging at vari-
ous rates, all of the effects can be easily lumped into one
easy to use term, C
PD
.
Calculation of transient power due to load capacitance is a
little more complex since each output is switched at one half
the rate of the previous output: Taking this into account the
complete expression for power consumption is:
This reduces to:
P
TOTAL
= (C
PD
+ C
L
) V
CC
2 f + I
L
V
CC
From the data sheet C
= 90 pF and I
L
= 0.05 μA. Using
Figure 6 total power is then:
This demonstrates that with more complex devices the con-
cept of C
greatly simplifies the calculation of total power
consumption. It becomes an easy task to compute power for
different voltages and frequencies by use of Figure 6and the
equations above.
PROPAGATION DELAY
Propagation delay for all 54C/74C devices is guaranteed
with a load of 50 pF and input rise and fall times of 20 ns.A
50 pF load was chosen, instead of 15 pF as in the 4000 se-
ries, because it is representative of loads commonly seen in
CMOS systems. A good rule of thumb, in designing with
CMOS, is to assume 10 pF of interwiring capacitance. Oper-
ating at the specified propagation delay would allow 5 pF
AN006021-9
FIGURE 6. Normalized Typical Power
Consumption vs Frequency
www.fairchildsemi.com
4
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