- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378403 > AN-136 (Integrated Device Technology, Inc.) A NEW GENERATION OF TAG SRAMS?THE IDT71215 AND PDF資料下載
參數(shù)資料
| 型號： | AN-136 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | A NEW GENERATION OF TAG SRAMS?THE IDT71215 AND |
| 中文描述： | 作為TAG SRAM的呢？IDT71215和新一代 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 103K |
| 代理商： | AN-136 |
11
A NEW GENERATION OF TAG SRAMS—THE IDT71215 AND IDT71216
APPLICATION NOTE AN-136
ADDR
DATA
A
0
- A
11
A
0
- A
28
DH
0
- DH
31
, DL
0
- DL
31
, and DP
0
- DP
7
A
13
- A
28
PowerPC
A
D
S
CHIP SET
CACHE READ
and WRITE
MAIN MEMORY READ/WRITE
TA
RESET
TT1
A
13
- A
26
TA
TAG (11:0)
ADDR (13:0)
I/Os
ADDR
CS2
CS1
64K x 18
BURST
SRAM
D
(2) IDT71216
TAG RAM
TAH
TAOE
TAH
3
3
WES
WET
OET
WES
WET
OET
TAOE
PWRDN
PWRDN
MATCH
STATUS
STATUS
MATCH
STATUSout
STATUSin
SFUNC
TT1
TAIN
CS2
CS1
OES
TA
VARIOUS CONTROL SIGNALS
V
CC
CS2
CS1
A
12
I/Os
ADDR
64K x 18
BURST
SRAM
V
CC
CS2
CS1
A
12
D
3176 drw 13
Figure 13 shows a 1MB cache for the PowerPC using the
71216. The implementation is essentially the same as for
512KB, but with two 71216 Tags and two banks of data
SRAMs. Except for
CS1
and CS2, all the same signals that
were connected to the first Tag RAM should be connected to
the same pins of the second Tag RAM. The least significant
tag bit of the 512KB cache is used to select between the two
Tag RAMs of the 1MB cache. The same is true for the two
banks of data SRAMs. The tag field then shifts one bit in the
direction of the more significant address bits. Please note that
the PowerPC and Intel processors do not have the same
address sequence. A0 is the MSB for the PowerPC while A31
is the MSB for Intel's processors.
Figure 13: PowerPC / 71216 Example of 1 MB Cache
It is also possible to double the size of the cache and
cached address space without doubling up the Tag RAMs.
This can be done by doubling the line size of the cache - from
32 bytes to 64 bytes, for example. It is not necessary to have
the same line size for both the primary and secondary caches,
though it does simplify the cache controller. A more detailed
discussion of this topic is beyond the scope of this application
note.
The CLK pin should be driven by the same clock that drives
the CPU. Although there is no standard for clock skew
tolerances between devices, a recommended target is
±
1nS.
MESI PROTOCOL IMPLEMENTATION
MESI is a cache coherency protocol, implemented in the
primary cache of both the PowerPC 601 and the Pentium
Processor. With the 71215/16, it is now practical to also
implement MESI for the L2 cache. The acronym stands for
Modified (write-back data that is dirty), Exclusive (clean write-
back data that can later transition to Modified), Shared (write-
through data which cannot become Modified) and Invalid. In
short, it allows for cache lines to be individually marked as
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AN-242 | LJT 18C 18#20 SKT RECP |
| AN-40 | Application Note 40 |
| AN-5002 | LJT 18C 18#20 SKT WALL RECP |
| AN-5025 | Applications Using the GTLP10B320 |
| AN-5026 | Circular Connector; No. of Contacts:19; Series:MS27656; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:15-19 RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AN137 | 制造商:SILABS 制造商全稱:SILABS 功能描述:LITHIUM ION BATTERY CHARGER USING C8051F300 |
| AN1375-521P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AN0625-521P |
| AN1393 | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:Dual Comparators |
| AN1393(AN6914) | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:Dual Comparators |
| AN1393S | 制造商:Panasonic Industrial Company 功能描述:IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。